Added support for RV32D and RV64D instructions
This commit is contained in:
Santosh Raghav Srivatsan
@@ -59,6 +59,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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Word func3 = instr.getFunc3();
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Word func6 = instr.getFunc6();
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Word func7 = instr.getFunc7();
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Word func2 = instr.getFunc2();
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auto opcode = instr.getOpcode();
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int rdest = instr.getRDest();
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@@ -346,8 +347,8 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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rd_write = true;
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break;
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case L_INST: {
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DoubleWord memAddr = ((rsdata[0] + immsrc) & 0xFFFFFFFC); // DoubleWord aligned
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DoubleWord shift_by = ((rsdata[0] + immsrc) & 0x00000003) * 8;
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DoubleWord memAddr = ((rsdata[0] + immsrc) & 0xFFFFFFF8); // DoubleWord aligned
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DoubleWord shift_by = ((rsdata[0] + immsrc) & 0x00000007) * 8;
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DoubleWord data_read = core_->dcache_read(memAddr, 8);
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D(3, "LOAD MEM: ADDRESS=0x" << std::hex << memAddr << ", DATA=0x" << data_read);
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switch (func3) {
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@@ -583,8 +584,13 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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DoubleWord memAddr = rsdata[0] + immsrc;
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DoubleWord data_read = core_->dcache_read(memAddr, 4);
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D(3, "LOAD MEM: ADDRESS=0x" << std::hex << memAddr << ", DATA=0x" << data_read);
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// simx64
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rddata = data_read | 0xFFFFFFFF00000000;
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} else if (func3 == 0x3) {
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// RV32D: FLD
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DoubleWord memAddr = ((rsdata[0] + immsrc) & 0xFFFFFFF8);
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DoubleWord data_read = core_->dcache_read(memAddr, 8);
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D(3, "LOAD MEM: ADDRESS=0x" << std::hex << memAddr << ", DATA=0x" << data_read);
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rddata = data_read;
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} else {
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D(3, "Executing vector load");
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D(3, "lmul: " << vtype_.vlmul << " VLEN:" << (core_->arch().vsize() * 8) << "sew: " << vtype_.vsew);
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@@ -615,9 +621,15 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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break;
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case (FS | VS):
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if (func3 == 0x2) {
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// RV32F: FSW
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DoubleWord memAddr = rsdata[0] + immsrc;
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core_->dcache_write(memAddr, rsdata[1], 4);
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D(3, "STORE MEM: ADDRESS=0x" << std::hex << memAddr);
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} else if (func3 == 0x3){
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// RV32D: FSD
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DoubleWord memAddr = rsdata[0] + immsrc;
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core_->dcache_write(memAddr, rsdata[1], 8);
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D(3, "STORE MEM: ADDRESS=0x" << std::hex << memAddr);
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} else {
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for (int i = 0; i < vl_; i++) {
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DoubleWord memAddr = rsdata[0] + (i * vtype_.vsew / 8);
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@@ -639,31 +651,59 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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uint32_t frm = get_fpu_rm(func3, core_, t, id_);
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uint32_t fflags = 0;
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switch (func7) {
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case 0x00: // RV32F: FADD
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case 0x00: // RV32F: FADD.S
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rddata = rv_fadd(rsdata[0], rsdata[1], frm, &fflags);
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break;
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case 0x04: // RV32F: FSUB
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case 0x01: // RV32D: FADD.D
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rddata = rv_fadd_d(rsdata[0], rsdata[1], frm, &fflags);
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break;
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case 0x04: // RV32F: FSUB.S
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rddata = rv_fsub(rsdata[0], rsdata[1], frm, &fflags);
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break;
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case 0x08: // RV32F: FMUL
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case 0x05: // RV32D: FSUB.D
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rddata = rv_fsub_d(rsdata[0], rsdata[1], frm, &fflags);
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break;
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case 0x08: // RV32F: FMUL.S
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rddata = rv_fmul(rsdata[0], rsdata[1], frm, &fflags);
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break;
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case 0x0c: // RV32F: FDIV
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case 0x09: // RV32D: FMUL.D
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rddata = rv_fmul_d(rsdata[0], rsdata[1], frm, &fflags);
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break;
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case 0x0c: // RV32F: FDIV.S
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rddata = rv_fdiv(rsdata[0], rsdata[1], frm, &fflags);
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break;
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case 0x2c: // RV32F: FSQRT
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case 0x0d: // RV32D: FDIV.D
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rddata = rv_fdiv_d(rsdata[0], rsdata[1], frm, &fflags);
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break;
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case 0x2c: // RV32F: FSQRT.S
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rddata = rv_fsqrt(rsdata[0], frm, &fflags);
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break;
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case 0x2d: // RV32D: FSQRT.D
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rddata = rv_fsqrt_d(rsdata[0], frm, &fflags);
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break;
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case 0x10:
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switch (func3) {
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case 0: // RV32F: FSGNJ.S
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rddata = rv_fsgnj(rsdata[0], rsdata[1]);
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rddata = rv_fsgnj((Word)rsdata[0], (Word)rsdata[1]) | 0xFFFFFFFF00000000;
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break;
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case 1: // RV32F: FSGNJN.S
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rddata = rv_fsgnjn(rsdata[0], rsdata[1]);
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rddata = rv_fsgnjn((Word)rsdata[0], (Word)rsdata[1]) | 0xFFFFFFFF00000000;
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break;
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case 2: // RV32F: FSGNJX.S
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rddata = rv_fsgnjx(rsdata[0], rsdata[1]);
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rddata = rv_fsgnjx((Word)rsdata[0], (Word)rsdata[1]) | 0xFFFFFFFF00000000;
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break;
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}
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break;
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case 0x11:
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switch (func3) {
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case 0: // RV32D: FSGNJ.D
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rddata = rv_fsgnj_d(rsdata[0], rsdata[1]);
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break;
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case 1: // RV32D: FSGNJN.D
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rddata = rv_fsgnjn_d(rsdata[0], rsdata[1]);
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break;
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case 2: // RV32D: FSGNJX.D
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rddata = rv_fsgnjx_d(rsdata[0], rsdata[1]);
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break;
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}
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break;
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@@ -676,6 +716,19 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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rddata = rv_fmin(rsdata[0], rsdata[1], &fflags);
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}
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break;
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case 0x15:
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if (func3) {
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// RV32D: FMAX.D
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rddata = rv_fmax_d(rsdata[0], rsdata[1], &fflags);
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} else {
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// RV32D: FMIN.D
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rddata = rv_fmin_d(rsdata[0], rsdata[1], &fflags);
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}
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break;
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case 0x20: rddata = rv_dtof(rsdata[0]);
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break;
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case 0x21: rddata = rv_ftod(rsdata[0]);
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break;
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case 0x60:
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switch(rsrc1) {
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case 0:
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@@ -696,6 +749,26 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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break;
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}
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break;
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case 0x61:
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switch(rsrc1) {
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case 0:
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// RV32D: FCVT.W.D
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rddata = signExt(rv_ftoi_d(rsdata[0], frm, &fflags), 32, 0xFFFFFFFF);
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break;
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case 1:
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// RV32D: FCVT.WU.D
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rddata = signExt(rv_ftou_d(rsdata[0], frm, &fflags), 32, 0xFFFFFFFF);
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break;
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case 2:
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// RV64D: FCVT.L.D
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rddata = rv_ftol_d(rsdata[0], frm, &fflags);
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break;
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case 3:
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// RV64D: FCVT.LU.D
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rddata = rv_ftolu_d(rsdata[0], frm, &fflags);
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break;
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}
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break;
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case 0x70:
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if (func3) {
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// RV32F: FCLASS.S
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@@ -705,6 +778,15 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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rddata = signExt((Word)rsdata[0], 32, 0xFFFFFFFF);
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}
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break;
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case 0x71:
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if (func3) {
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// RV32D: FCLASS.D
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rddata = rv_fclss_d(rsdata[0]);
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} else {
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// RV64D: FMV.X.D
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rddata = rsdata[0];
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}
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break;
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case 0x50:
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switch(func3) {
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case 0:
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@@ -719,7 +801,22 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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// RV32F: FEQ.S
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rddata = rv_feq(rsdata[0], rsdata[1], &fflags);
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break;
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} break;
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} break;
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case 0x51:
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switch(func3) {
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case 0:
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// RV32D: FLE.D
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rddata = rv_fle_d(rsdata[0], rsdata[1], &fflags);
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break;
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case 1:
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// RV32D: FLT.D
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rddata = rv_flt_d(rsdata[0], rsdata[1], &fflags);
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break;
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case 2:
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// RV32D: FEQ.D
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rddata = rv_feq_d(rsdata[0], rsdata[1], &fflags);
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break;
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} break;
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case 0x68:
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switch(rsrc1) {
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case 0:
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@@ -740,10 +837,34 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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break;
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}
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break;
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case 0x69:
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switch(rsrc1) {
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case 0:
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// RV32D: FCVT.D.W
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rddata = rv_itof_d(rsdata[0], frm, &fflags);
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break;
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case 1:
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// RV32F: FCVT.D.WU
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rddata = rv_utof_d(rsdata[0], frm, &fflags);
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break;
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case 2:
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// RV64D: FCVT.D.L
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rddata = rv_ltof_d(rsdata[0], frm, &fflags);
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break;
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case 3:
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// RV64D: FCVT.D.LU
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rddata = rv_lutof_d(rsdata[0], frm, &fflags);
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break;
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}
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break;
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case 0x78:
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// RV32F: FMV.W.X
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rddata = rsdata[0];
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break;
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case 0x79:
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// RV64D: FMV.D.X
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rddata = rsdata[0];
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break;
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}
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update_fcrs(fflags, core_, t, id_);
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rd_write = true;
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@@ -757,20 +878,36 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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Word fflags = 0;
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switch (opcode) {
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case FMADD:
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// RV32F: FMADD
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rddata = rv_fmadd(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
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if (func2)
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// RV32D: FMADD.D
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rddata = rv_fmadd_d(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
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else
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// RV32F: FMADD.S
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rddata = rv_fmadd(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
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break;
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case FMSUB:
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// RV32F: FMSUB
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rddata = rv_fmsub(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
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if (func2)
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// RV32D: FMSUB.D
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rddata = rv_fmsub_d(rsdata[0],rsdata[1], rsdata[2], frm, &fflags);
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else
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// RV32F: FMSUB.S
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rddata = rv_fmsub(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
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break;
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case FMNMADD:
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// RV32F: FNMADD
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rddata = rv_fnmadd(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
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if (func2)
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// RV32D: FNMADD.D
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rddata = rv_fnmadd_d(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
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else
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// RV32F: FNMADD.S
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rddata = rv_fnmadd(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
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break;
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case FMNMSUB:
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// RV32F: FNMSUB
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rddata = rv_fnmsub(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
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if (func2)
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// RV32D: FNMSUB.D
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rddata = rv_fnmsub_d(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
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else
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// RV32F: FNMSUB.S
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rddata = rv_fnmsub(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
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break;
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default:
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break;
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