From bcb95147992dde8eaeb895a87f72239191b6f1d0 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 14 May 2020 11:01:41 -0400 Subject: [PATCH] snooping response handling fix --- driver/tests/basic/Makefile | 10 +-- driver/tests/basic/common.h | 2 +- driver/tests/basic/kernel.bin | Bin 6548 -> 6548 bytes driver/tests/demo/Makefile | 10 +-- hw/rtl/VX_config.vh | 34 ++------ hw/rtl/VX_define.vh | 23 ++++- hw/rtl/VX_dmem_ctrl.v | 17 ++-- hw/rtl/Vortex.v | 4 +- hw/rtl/Vortex_Cluster.v | 1 + hw/rtl/Vortex_Socket.v | 3 +- hw/rtl/cache/VX_bank.v | 131 ++++++++++++++++------------- hw/rtl/cache/VX_cache.v | 11 ++- hw/rtl/cache/VX_cache_config.vh | 8 +- hw/rtl/cache/VX_cache_miss_resrv.v | 10 ++- hw/rtl/cache/VX_fill_invalidator.v | 8 +- hw/rtl/cache/VX_snp_forwarder.v | 12 +-- simX/test_benchmark.sh | 2 + simX/test_riscv.sh | 2 + simX/test_runtime.sh | 2 + simX/test_vec.sh | 2 + 20 files changed, 166 insertions(+), 126 deletions(-) diff --git a/driver/tests/basic/Makefile b/driver/tests/basic/Makefile index 46be3db4..123d657c 100644 --- a/driver/tests/basic/Makefile +++ b/driver/tests/basic/Makefile @@ -27,14 +27,11 @@ PROJECT = basic SRCS = basic.cpp -all: $(PROJECT) +all: $(PROJECT) kernel.bin kernel.dump kernel.dump: kernel.elf $(VX_DMP) -D kernel.elf > kernel.dump -kernel.hex: kernel.elf - $(VX_CPY) -O ihex kernel.elf kernel.hex - kernel.bin: kernel.elf $(VX_CPY) -O binary kernel.elf kernel.bin @@ -60,7 +57,10 @@ run-simx: $(PROJECT) $(CXX) $(CXXFLAGS) -MM $^ > .depend; clean: - rm -rf $(PROJECT) *.o .depend + rm -rf $(PROJECT) *.o .depend + +clean-all: + rm -rf $(PROJECT) *.o *.elf *.bin *.dump .depend ifneq ($(MAKECMDGOALS),clean) -include .depend diff --git a/driver/tests/basic/common.h b/driver/tests/basic/common.h index 9e178034..97310d5a 100644 --- a/driver/tests/basic/common.h +++ b/driver/tests/basic/common.h @@ -3,6 +3,6 @@ #define DEV_MEM_SRC_ADDR 0x10000000 #define DEV_MEM_DST_ADDR 0x20000000 -#define NUM_BLOCKS 4 +#define NUM_BLOCKS 16 #endif \ No newline at end of file diff --git a/driver/tests/basic/kernel.bin b/driver/tests/basic/kernel.bin index 7dd503d35b4a5519b993ded72172b6b1516ac310..05143e854c7bbbc85db1ec86e918a61249e99d98 100755 GIT binary patch delta 12 TcmbPYJjHlIG9$;v6az^B9E=0$ delta 12 TcmbPYJjHlIG9%N*6az^B9Bu>S diff --git a/driver/tests/demo/Makefile b/driver/tests/demo/Makefile index 7efef96b..321a5217 100644 --- a/driver/tests/demo/Makefile +++ b/driver/tests/demo/Makefile @@ -25,14 +25,11 @@ PROJECT = demo SRCS = demo.cpp -all: $(PROJECT) +all: $(PROJECT) kernel.bin kernel.dump kernel.dump: kernel.elf $(VX_DMP) -D kernel.elf > kernel.dump -kernel.hex: kernel.elf - $(VX_CPY) -O ihex kernel.elf kernel.hex - kernel.bin: kernel.elf $(VX_CPY) -O binary kernel.elf kernel.bin @@ -58,7 +55,10 @@ run-simx: $(PROJECT) $(CXX) $(CXXFLAGS) -MM $^ > .depend; clean: - rm -rf $(PROJECT) *.o *.dump .depend + rm -rf $(PROJECT) *.o .depend + +clean-all: + rm -rf $(PROJECT) *.o *.elf *.bin *.dump .depend ifneq ($(MAKECMDGOALS),clean) -include .depend diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index 123e0a01..02071526 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -55,6 +55,10 @@ `define L2_ENABLE (`NUM_CORES > 1) `endif +`ifndef L3_ENABLE +`define L3_ENABLE (`NUM_CLUSTERS > 1) +`endif + `define CSR_LTID 12'h020 `define CSR_LWID 12'h021 `define CSR_GTID 12'h022 @@ -113,7 +117,7 @@ // Snoop Req Queue Size `ifndef DSNRQ_SIZE -`define DSNRQ_SIZE 32 +`define DSNRQ_SIZE 16 `endif // Core Writeback Queue Size @@ -138,7 +142,7 @@ // Snoop Rsp Queue Size `ifndef DSRPQ_SIZE -`define DSRPQ_SIZE 32 +`define DSRPQ_SIZE 8 `endif // Prefetcher @@ -197,11 +201,6 @@ `define IDFPQ_SIZE 32 `endif -// Snoop Req Queue Size -`ifndef ISNRQ_SIZE -`define ISNRQ_SIZE 32 -`endif - // Core Writeback Queue Size `ifndef ICWBQ_SIZE `define ICWBQ_SIZE `IREQQ_SIZE @@ -222,11 +221,6 @@ `define ILLVQ_SIZE 16 `endif -// Snoop Rsp Queue Size -`ifndef ISRPQ_SIZE -`define ISRPQ_SIZE 8 -`endif - // Prefetcher `ifndef IPRFQ_SIZE `define IPRFQ_SIZE 32 @@ -283,11 +277,6 @@ `define SDFPQ_SIZE 0 `endif -// Snoop Req Queue Size -`ifndef SSNRQ_SIZE -`define SSNRQ_SIZE 16 -`endif - // Core Writeback Queue Size `ifndef SCWBQ_SIZE `define SCWBQ_SIZE `SREQQ_SIZE @@ -308,11 +297,6 @@ `define SLLVQ_SIZE 16 `endif -// Snoop Rsp Queue Size -`ifndef SSRPQ_SIZE -`define SSRPQ_SIZE 16 -`endif - // Prefetcher `ifndef SPRFQ_SIZE `define SPRFQ_SIZE 4 @@ -371,7 +355,7 @@ // Snoop Req Queue Size `ifndef L2SNRQ_SIZE -`define L2SNRQ_SIZE 32 +`define L2SNRQ_SIZE 16 `endif // Core Writeback Queue Size @@ -396,7 +380,7 @@ // Snoop Rsp Queue Size `ifndef L2SRPQ_SIZE -`define L2SRPQ_SIZE 32 +`define L2SRPQ_SIZE 8 `endif // Prefetcher @@ -457,7 +441,7 @@ // Snoop Req Queue Size `ifndef L3SNRQ_SIZE -`define L3SNRQ_SIZE 32 +`define L3SNRQ_SIZE 16 `endif // Core Writeback Queue Size diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index f4e8f537..2f088e60 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -30,11 +30,11 @@ endgenerate `define CLOG2(x) $clog2(x) -`define FLOG2(x) ($clog2(x) - (((1 << $clog2(x)) > x) ? 1 : 0)) -`define LOG2UP(x) ((x > 1) ? $clog2(x) : 1) +`define FLOG2(x) ($clog2(x) - (((1 << $clog2(x)) > (x)) ? 1 : 0)) +`define LOG2UP(x) (((x) > 1) ? $clog2(x) : 1) -`define MIN(x, y) ((x < y) ? x : y); -`define MAX(x, y) ((x > y) ? x : y); +`define MIN(x, y) ((x < y) ? (x) : (y)) +`define MAX(x, y) ((x > y) ? (x) : (y)) /////////////////////////////////////////////////////////////////////////////// @@ -126,6 +126,9 @@ ////////////////////////// Dcache Configurable Knobs ////////////////////////// +// Cache ID +`define DCACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 0) + // DRAM request data bits `define DDRAM_LINE_WIDTH (`DBANK_LINE_SIZE * 8) @@ -143,6 +146,9 @@ ////////////////////////// Icache Configurable Knobs ////////////////////////// +// Cache ID +`define ICACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 1) + // DRAM request data bits `define IDRAM_LINE_WIDTH (`IBANK_LINE_SIZE * 8) @@ -157,6 +163,9 @@ ////////////////////////// SM Configurable Knobs ////////////////////////////// +// Cache ID +`define SCACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 3) + // DRAM request data bits `define SDRAM_LINE_WIDTH (`SBANK_LINE_SIZE * 8) @@ -171,6 +180,9 @@ ////////////////////////// L2cache Configurable Knobs ///////////////////////// +// Cache ID +`define L2CACHE_ID (`L3_ENABLE ? 1 : 0) + // DRAM request data bits `define L2DRAM_LINE_WIDTH (`L2BANK_LINE_SIZE * 8) @@ -188,6 +200,9 @@ ////////////////////////// L3cache Configurable Knobs ///////////////////////// +// Cache ID +`define L3CACHE_ID 0 + // DRAM request data bits `define L3DRAM_LINE_WIDTH (`L3BANK_LINE_SIZE * 8) diff --git a/hw/rtl/VX_dmem_ctrl.v b/hw/rtl/VX_dmem_ctrl.v index 6531cdc7..9c63a85d 100644 --- a/hw/rtl/VX_dmem_ctrl.v +++ b/hw/rtl/VX_dmem_ctrl.v @@ -1,6 +1,8 @@ `include "VX_define.vh" -module VX_dmem_ctrl ( +module VX_dmem_ctrl # ( + parameter CORE_ID = 0 +) ( input wire clk, input wire reset, @@ -36,7 +38,7 @@ module VX_dmem_ctrl ( .CORE_TAG_ID_BITS(`CORE_TAG_ID_BITS) ) dcache_core_rsp_qual_if(), smem_core_rsp_if(); - // use "case equality" to handle uninitialized address value + // use "case equality" to handle uninitialized entry wire smem_select = ((dcache_core_req_if.core_req_addr[0][31:24] == `SHARED_MEM_TOP_ADDR) === 1'b1); VX_dcache_io_arb dcache_io_arb ( @@ -50,6 +52,7 @@ module VX_dmem_ctrl ( ); VX_cache #( + .CACHE_ID (`SCACHE_ID), .CACHE_SIZE (`SCACHE_SIZE), .BANK_LINE_SIZE (`SBANK_LINE_SIZE), .NUM_BANKS (`SNUM_BANKS), @@ -59,12 +62,12 @@ module VX_dmem_ctrl ( .REQQ_SIZE (`SREQQ_SIZE), .MRVQ_SIZE (`SMRVQ_SIZE), .DFPQ_SIZE (`SDFPQ_SIZE), - .SNRQ_SIZE (`SSNRQ_SIZE), + .SNRQ_SIZE (0), .CWBQ_SIZE (`SCWBQ_SIZE), .DWBQ_SIZE (`SDWBQ_SIZE), .DFQQ_SIZE (`SDFQQ_SIZE), .LLVQ_SIZE (`SLLVQ_SIZE), - .SRPQ_SIZE (`SSRPQ_SIZE), + .SRPQ_SIZE (0), .PRFQ_SIZE (`SPRFQ_SIZE), .PRFQ_STRIDE (`SPRFQ_STRIDE), .FILL_INVALIDAOR_SIZE (`SFILL_INVALIDAOR_SIZE), @@ -133,6 +136,7 @@ module VX_dmem_ctrl ( ); VX_cache #( + .CACHE_ID (`DCACHE_ID), .CACHE_SIZE (`DCACHE_SIZE), .BANK_LINE_SIZE (`DBANK_LINE_SIZE), .NUM_BANKS (`DNUM_BANKS), @@ -217,6 +221,7 @@ module VX_dmem_ctrl ( ); VX_cache #( + .CACHE_ID (`ICACHE_ID), .CACHE_SIZE (`ICACHE_SIZE), .BANK_LINE_SIZE (`IBANK_LINE_SIZE), .NUM_BANKS (`INUM_BANKS), @@ -226,12 +231,12 @@ module VX_dmem_ctrl ( .REQQ_SIZE (`IREQQ_SIZE), .MRVQ_SIZE (`IMRVQ_SIZE), .DFPQ_SIZE (`IDFPQ_SIZE), - .SNRQ_SIZE (`ISNRQ_SIZE), + .SNRQ_SIZE (0), .CWBQ_SIZE (`ICWBQ_SIZE), .DWBQ_SIZE (`IDWBQ_SIZE), .DFQQ_SIZE (`IDFQQ_SIZE), .LLVQ_SIZE (`ILLVQ_SIZE), - .SRPQ_SIZE (`ISRPQ_SIZE), + .SRPQ_SIZE (0), .PRFQ_SIZE (`IPRFQ_SIZE), .PRFQ_STRIDE (`IPRFQ_STRIDE), .FILL_INVALIDAOR_SIZE (`IFILL_INVALIDAOR_SIZE), diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index 0ebe6ba8..1993a221 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -241,7 +241,9 @@ module Vortex #( .ebreak (ebreak) ); - VX_dmem_ctrl dmem_ctrl ( + VX_dmem_ctrl #( + .CORE_ID(CORE_ID) + ) dmem_ctrl ( .clk (clk), .reset (reset), diff --git a/hw/rtl/Vortex_Cluster.v b/hw/rtl/Vortex_Cluster.v index 7b48c01d..f78b21e3 100644 --- a/hw/rtl/Vortex_Cluster.v +++ b/hw/rtl/Vortex_Cluster.v @@ -238,6 +238,7 @@ module Vortex_Cluster #( assign l2_core_rsp_ready = (& per_core_D_dram_rsp_ready) && (& per_core_I_dram_rsp_ready); VX_cache #( + .CACHE_ID (`L2CACHE_ID), .CACHE_SIZE (`L2CACHE_SIZE), .BANK_LINE_SIZE (`L2BANK_LINE_SIZE), .NUM_BANKS (`L2NUM_BANKS), diff --git a/hw/rtl/Vortex_Socket.v b/hw/rtl/Vortex_Socket.v index 2001e191..1bfa9777 100644 --- a/hw/rtl/Vortex_Socket.v +++ b/hw/rtl/Vortex_Socket.v @@ -53,7 +53,7 @@ module Vortex_Socket ( if (`NUM_CLUSTERS == 1) begin Vortex_Cluster #( - .CLUSTER_ID(0) + .CLUSTER_ID(`L3CACHE_ID) ) Vortex_Cluster ( .clk (clk), .reset (reset), @@ -244,6 +244,7 @@ module Vortex_Socket ( assign l3_core_rsp_ready = (& per_cluster_dram_rsp_ready); VX_cache #( + .CACHE_ID (0), .CACHE_SIZE (`L3CACHE_SIZE), .BANK_LINE_SIZE (`L3BANK_LINE_SIZE), .NUM_BANKS (`L3NUM_BANKS), diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 9b558c80..628971a0 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -1,6 +1,8 @@ `include "VX_cache_config.vh" -`include "VX_define.vh" + module VX_bank #( + parameter CACHE_ID = 0, + parameter BANK_ID = 0, // Size of cache in bytes parameter CACHE_SIZE = 0, // Size of line inside a bank in bytes @@ -57,8 +59,8 @@ module VX_bank #( // Snooping request tag width parameter SNP_REQ_TAG_WIDTH = 0 ) ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, // Core Request input wire [NUM_REQUESTS-1:0] core_req_valids, @@ -205,7 +207,7 @@ module VX_bank #( wire [`LINE_ADDR_WIDTH-1:0] mrvq_addr_st0; wire [`BASE_ADDR_BITS-1:0] mrvq_wsel_st0; wire [`WORD_WIDTH-1:0] mrvq_writeword_st0; - wire [CORE_TAG_WIDTH-1:0] mrvq_tag_st0; + wire [`REQ_TAG_WIDTH-1:0] mrvq_tag_st0; wire [`BYTE_EN_BITS-1:0] mrvq_mem_read_st0; wire [`BYTE_EN_BITS-1:0] mrvq_mem_write_st0; wire mrvq_is_snp_st0; @@ -224,7 +226,7 @@ module VX_bank #( wire[`BASE_ADDR_BITS-1:0] miss_add_wsel; wire[`WORD_WIDTH-1:0] miss_add_data; wire[`REQS_BITS-1:0] miss_add_tid; - wire[CORE_TAG_WIDTH-1:0] miss_add_tag; + wire[`REQ_TAG_WIDTH-1:0] miss_add_tag; wire[`BYTE_EN_BITS-1:0] miss_add_mem_read; wire[`BYTE_EN_BITS-1:0] miss_add_mem_write; @@ -247,10 +249,6 @@ module VX_bank #( is_fill_in_pipe = 1; end end - - // if (is_fill_st2) begin - // is_fill_in_pipe = 1; - // end end assign mrvq_pop = mrvq_valid_st0 && !stall_bank_pipe; @@ -270,24 +268,23 @@ module VX_bank #( wire qual_going_to_write_st0; wire qual_is_snp_st0; - wire valid_st1 [STAGE_1_CYCLES-1:0]; - wire [`LINE_ADDR_WIDTH-1:0] addr_st1 [STAGE_1_CYCLES-1:0]; - wire [`WORD_SELECT_ADDR_END:0] wsel_st1 [STAGE_1_CYCLES-1:0]; - wire [`WORD_WIDTH-1:0] writeword_st1 [STAGE_1_CYCLES-1:0]; - wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0]; - wire [`BANK_LINE_WIDTH-1:0] writedata_st1 [STAGE_1_CYCLES-1:0]; - wire [SNP_REQ_TAG_WIDTH-1:0] snrq_tag_st1 [STAGE_1_CYCLES-1:0]; - wire is_snp_st1 [STAGE_1_CYCLES-1:0]; - wire from_mrvq_st1 [STAGE_1_CYCLES-1:0]; + wire valid_st1 [STAGE_1_CYCLES-1:0]; + wire [`LINE_ADDR_WIDTH-1:0] addr_st1 [STAGE_1_CYCLES-1:0]; + wire [`WORD_SELECT_ADDR_END:0] wsel_st1 [STAGE_1_CYCLES-1:0]; + wire [`WORD_WIDTH-1:0] writeword_st1 [STAGE_1_CYCLES-1:0]; + wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0]; + wire [`BANK_LINE_WIDTH-1:0] writedata_st1 [STAGE_1_CYCLES-1:0]; + wire is_snp_st1 [STAGE_1_CYCLES-1:0]; + wire from_mrvq_st1 [STAGE_1_CYCLES-1:0]; assign qual_is_fill_st0 = dfpq_pop; assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop || snrq_pop; - assign qual_addr_st0 = dfpq_pop ? dfpq_addr_st0 : - mrvq_pop ? mrvq_addr_st0 : + assign qual_addr_st0 = dfpq_pop ? dfpq_addr_st0 : + mrvq_pop ? mrvq_addr_st0 : reqq_pop ? reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] : - snrq_pop ? snrq_addr_st0 : + snrq_pop ? snrq_addr_st0 : 0; assign qual_wsel_st0 = reqq_pop ? reqq_req_addr_st0[`BASE_ADDR_BITS-1:0] : @@ -296,48 +293,48 @@ module VX_bank #( assign qual_writedata_st0 = dfpq_pop ? dfpq_filldata_st0 : 57; - assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_tag_st0 , mrvq_mem_read_st0, mrvq_mem_write_st0, mrvq_tid_st0} : - reqq_pop ? {reqq_req_tag_st0, reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} : + assign qual_inst_meta_st0 = mrvq_pop ? {`REQ_TAG_WIDTH'(mrvq_tag_st0) , mrvq_mem_read_st0, mrvq_mem_write_st0, mrvq_tid_st0} : + reqq_pop ? {`REQ_TAG_WIDTH'(reqq_req_tag_st0), reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} : + snrq_pop ? {`REQ_TAG_WIDTH'(snrq_tag_st0), `BYTE_EN_BITS'(0), `BYTE_EN_BITS'(0), `REQS_BITS'(0)} : 0; assign qual_going_to_write_st0 = dfpq_pop ? 1 : (mrvq_pop && (mrvq_mem_write_st0 != `BYTE_EN_NO)) ? 1 : (reqq_pop && (reqq_req_mem_write_st0 != `BYTE_EN_NO)) ? 1 : - (snrq_pop) ? 1 : - 0; + 0; assign qual_is_snp_st0 = mrvq_pop ? mrvq_is_snp_st0 : snrq_pop ? 1 : - 0; + 0; assign qual_writeword_st0 = mrvq_pop ? mrvq_writeword_st0 : reqq_pop ? reqq_req_writeword_st0 : - 0; + 0; assign qual_from_mrvq_st0 = mrvq_pop; VX_generic_register #( - .N(1+ 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH + SNP_REQ_TAG_WIDTH) + .N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH) ) s0_1_c0 ( .clk (clk), .reset (reset), .stall (stall_bank_pipe), .flush (0), - .in ({qual_from_mrvq_st0, qual_is_snp_st0, snrq_tag_st0, qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_wsel_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}), - .out ({from_mrvq_st1[0] , is_snp_st1[0], snrq_tag_st1[0], going_to_write_st1[0], valid_st1[0], addr_st1[0], wsel_st1[0], writeword_st1[0], inst_meta_st1[0], is_fill_st1[0], writedata_st1[0]}) + .in ({qual_from_mrvq_st0, qual_is_snp_st0, qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_wsel_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}), + .out ({from_mrvq_st1[0] , is_snp_st1[0], going_to_write_st1[0], valid_st1[0], addr_st1[0], wsel_st1[0], writeword_st1[0], inst_meta_st1[0], is_fill_st1[0], writedata_st1[0]}) ); genvar i; for (i = 1; i < STAGE_1_CYCLES; i++) begin VX_generic_register #( - .N(1+ 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH + SNP_REQ_TAG_WIDTH) + .N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH) ) s0_1_cc ( .clk (clk), .reset(reset), .stall(stall_bank_pipe), .flush(0), - .in ({from_mrvq_st1[i-1], is_snp_st1[i-1], snrq_tag_st1[i-1], going_to_write_st1[i-1], valid_st1[i-1], addr_st1[i-1], wsel_st1[i-1], writeword_st1[i-1], inst_meta_st1[i-1], is_fill_st1[i-1], writedata_st1[i-1]}), - .out ({from_mrvq_st1[i] , is_snp_st1[i], snrq_tag_st1[i], going_to_write_st1[i], valid_st1[i], addr_st1[i], wsel_st1[i], writeword_st1[i], inst_meta_st1[i], is_fill_st1[i], writedata_st1[i]}) + .in ({from_mrvq_st1[i-1], is_snp_st1[i-1], going_to_write_st1[i-1], valid_st1[i-1], addr_st1[i-1], wsel_st1[i-1], writeword_st1[i-1], inst_meta_st1[i-1], is_fill_st1[i-1], writedata_st1[i-1]}), + .out ({from_mrvq_st1[i] , is_snp_st1[i], going_to_write_st1[i], valid_st1[i], addr_st1[i], wsel_st1[i], writeword_st1[i], inst_meta_st1[i], is_fill_st1[i], writedata_st1[i]}) ); end @@ -347,7 +344,7 @@ module VX_bank #( wire miss_st1e; wire dirty_st1e; `DEBUG_BEGIN - wire [CORE_TAG_WIDTH-1:0] tag_st1e; + wire [`REQ_TAG_WIDTH-1:0] tag_st1e; wire [`REQS_BITS-1:0] tid_st1e; `DEBUG_END wire [`BYTE_EN_BITS-1:0] mem_read_st1e; @@ -358,6 +355,7 @@ module VX_bank #( wire mrvq_init_ready_state_st1e; assign is_snp_st1e = is_snp_st1[STAGE_1_CYCLES-1]; + assign {tag_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1]; assign st2_pending_hazard_st1e = (miss_add_because_miss) && ((addr_st2 == addr_st1[STAGE_1_CYCLES-1]) && !is_fill_st2); @@ -419,32 +417,32 @@ module VX_bank #( wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st2; wire [`TAG_SELECT_BITS-1:0] readtag_st2; wire fill_saw_dirty_st2; - wire [SNP_REQ_TAG_WIDTH-1:0] snrq_tag_st2; wire is_snp_st2; wire snp_to_mrvq_st2; wire mrvq_init_ready_state_st2; VX_generic_register #( - .N(1+1+ 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + `REQ_INST_META_WIDTH + SNP_REQ_TAG_WIDTH) + .N(1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + `REQ_INST_META_WIDTH) ) st_1e_2 ( .clk (clk), .reset(reset), .stall(stall_bank_pipe), .flush(0), - .in ({mrvq_init_ready_state_st1e, snp_to_mrvq_st1e, is_snp_st1e, snrq_tag_st1[STAGE_1_CYCLES-1], fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}), - .out ({mrvq_init_ready_state_st2, snp_to_mrvq_st2 , is_snp_st2 , snrq_tag_st2, fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 }) + .in ({mrvq_init_ready_state_st1e, snp_to_mrvq_st1e, is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}), + .out ({mrvq_init_ready_state_st2, snp_to_mrvq_st2 , is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 }) ); - wire dram_fill_req_stall = (valid_st2 && miss_st2 && !invalidate_fill && ~dram_fill_req_ready); - wire cwbq_full; wire dwbq_push; + wire dwbq_pop; wire dwbq_empty; wire dwbq_full; - wire srpq_full; - wire invalidate_fill; + wire cwbq_full; + wire srpq_full; + + wire invalidate_fill; wire miss_add_is_snp; // Enqueue to miss reserv if it's a valid miss @@ -471,10 +469,12 @@ module VX_bank #( .WORD_SIZE (WORD_SIZE), .NUM_REQUESTS (NUM_REQUESTS), .MRVQ_SIZE (MRVQ_SIZE), - .CORE_TAG_WIDTH (CORE_TAG_WIDTH) + .CORE_TAG_WIDTH (CORE_TAG_WIDTH), + .SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH) ) cache_miss_resrv ( .clk (clk), .reset (reset), + // Enqueue .miss_add (miss_add), .miss_add_addr (miss_add_addr), @@ -493,8 +493,6 @@ module VX_bank #( .is_fill_st1 (is_fill_st1[STAGE_1_CYCLES-1]), .fill_addr_st1 (addr_st1[STAGE_1_CYCLES-1]), .pending_hazard (mrvq_pending_hazard_st1e), - // .is_fill_st1 (is_fill_st2), - // .fill_addr_st1 (addr_st2), // Dequeue .miss_resrv_pop (mrvq_pop), @@ -509,8 +507,8 @@ module VX_bank #( .miss_resrv_is_snp_st0 (mrvq_is_snp_st0) ); - wire cwbq_push_unqual = valid_st2 && !miss_st2 && !is_fill_st2 && !is_snp_st2; // Enqueue to CWB Queue + wire cwbq_push_unqual = valid_st2 && !miss_st2 && !is_fill_st2 && !is_snp_st2; wire cwbq_push = cwbq_push_unqual && !cwbq_full && (miss_add_mem_write == `BYTE_EN_NO) @@ -521,7 +519,7 @@ module VX_bank #( wire [`WORD_WIDTH-1:0] cwbq_data = readword_st2; wire [`REQS_BITS-1:0] cwbq_tid = miss_add_tid; - wire [CORE_TAG_WIDTH-1:0] cwbq_tag = miss_add_tag; + wire [CORE_TAG_WIDTH-1:0] cwbq_tag = CORE_TAG_WIDTH'(miss_add_tag); wire cwbq_empty; wire cwbq_pop; @@ -545,8 +543,8 @@ module VX_bank #( .full (cwbq_full) ); - wire dwbq_push_unqual = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2); // Enqueue to DWB Queue + wire dwbq_push_unqual = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2); assign dwbq_push = dwbq_push_unqual && !dwbq_full && !((snp_rsp_push_unqual && srpq_full) @@ -579,6 +577,8 @@ module VX_bank #( assign dram_wb_req_valid = !dwbq_empty; + assign dwbq_pop = dram_wb_req_valid && dram_wb_req_ready; + VX_generic_queue #( .DATAW(`LINE_ADDR_WIDTH + `BANK_LINE_WIDTH), .SIZE(DWBQ_SIZE) @@ -589,25 +589,30 @@ module VX_bank #( .push (dwbq_push), .data_in ({dwbq_req_addr, dwbq_req_data}), - .pop (dram_wb_req_ready), + .pop (dwbq_pop), .data_out({dram_wb_req_addr, dram_wb_req_data}), .empty (dwbq_empty), .full (dwbq_full) ); - wire snp_rsp_push; + wire srpq_push; + wire srpq_pop; wire srpq_empty; wire snp_rsp_push_unqual = is_snp_st2 && valid_st2 && !snp_to_mrvq_st2; - - assign snp_rsp_push = snp_rsp_push_unqual - && !srpq_full - && !((cwbq_push_unqual && cwbq_full) - || (dwbq_push_unqual && dwbq_full) - || (miss_add_unqual && mrvq_full) - || dram_fill_req_stall); - assign snp_rsp_valid = !srpq_empty; + wire [SNP_REQ_TAG_WIDTH-1:0] snrq_tag_st2 = SNP_REQ_TAG_WIDTH'(miss_add_tag); + + assign srpq_push = snp_rsp_push_unqual + && !srpq_full + && !((cwbq_push_unqual && cwbq_full) + || (dwbq_push_unqual && dwbq_full) + || (miss_add_unqual && mrvq_full) + || dram_fill_req_stall); + + assign srpq_pop = snp_rsp_valid && snp_rsp_ready; + + assign snp_rsp_valid = !srpq_empty; VX_generic_queue #( .DATAW(SNP_REQ_TAG_WIDTH), @@ -615,9 +620,9 @@ module VX_bank #( ) snp_rsp_queue ( .clk (clk), .reset (reset), - .push (snp_rsp_push), + .push (srpq_push), .data_in (snrq_tag_st2), - .pop (snp_rsp_ready), + .pop (srpq_pop), .data_out(snp_rsp_tag), .empty (srpq_empty), .full (srpq_full) @@ -629,4 +634,10 @@ module VX_bank #( || (miss_add_unqual && mrvq_full) || dram_fill_req_stall; + /*always_comb begin + if (1'($time & 1) && snp_rsp_push) begin + $display("*** %t: bank%01d:%01d snp rsp in: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, addr_st2, snrq_tag_st2); + end + end*/ + endmodule : VX_bank \ No newline at end of file diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index 92aa3fd9..93fb3996 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -1,6 +1,7 @@ `include "VX_cache_config.vh" module VX_cache #( + parameter CACHE_ID = 0, // Size of cache in bytes parameter CACHE_SIZE = 1024, // Size of line inside a bank in bytes @@ -305,7 +306,9 @@ module VX_cache #( assign per_bank_snp_rsp_tag[i] = curr_bank_snp_rsp_tag; assign curr_bank_snp_rsp_ready = per_bank_snp_rsp_ready[i]; - VX_bank #( + VX_bank #( + .BANK_ID (i), + .CACHE_ID (CACHE_ID), .CACHE_SIZE (CACHE_SIZE), .BANK_LINE_SIZE (BANK_LINE_SIZE), .NUM_BANKS (NUM_BANKS), @@ -432,5 +435,11 @@ module VX_cache #( .snp_rsp_tag (snp_rsp_tag), .snp_rsp_ready (snp_rsp_ready) ); + + /*always_comb begin + if (1'($time & 1) && snp_rsp_valid && snp_rsp_ready) begin + $display("*** %t: cache%01d snp rsp tag=%0h", $time, CACHE_ID, snp_rsp_tag); + end + end*/ endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_cache_config.vh b/hw/rtl/cache/VX_cache_config.vh index 8f79bdbf..bd2aeea2 100644 --- a/hw/rtl/cache/VX_cache_config.vh +++ b/hw/rtl/cache/VX_cache_config.vh @@ -3,11 +3,13 @@ `include "VX_define.vh" -// data tid tag read write base addr is_snp -`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQS_BITS + CORE_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `BASE_ADDR_BITS + 1) +`define REQ_TAG_WIDTH `MAX(CORE_TAG_WIDTH, SNP_REQ_TAG_WIDTH) + +// data tid tag read write base addr is_snp +`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQS_BITS + `REQ_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `BASE_ADDR_BITS + 1) // tag read write reqs -`define REQ_INST_META_WIDTH (CORE_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `REQS_BITS) +`define REQ_INST_META_WIDTH (`REQ_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `REQS_BITS) `define REQS_BITS `LOG2UP(NUM_REQUESTS) diff --git a/hw/rtl/cache/VX_cache_miss_resrv.v b/hw/rtl/cache/VX_cache_miss_resrv.v index 6714daec..dbe3665f 100644 --- a/hw/rtl/cache/VX_cache_miss_resrv.v +++ b/hw/rtl/cache/VX_cache_miss_resrv.v @@ -11,8 +11,10 @@ module VX_cache_miss_resrv #( parameter NUM_REQUESTS = 0, // Miss Reserv Queue Knob parameter MRVQ_SIZE = 0, - // caceh requests tag size - parameter CORE_TAG_WIDTH = 0 + // core request tag size + parameter CORE_TAG_WIDTH = 0, + // Snooping request tag width + parameter SNP_REQ_TAG_WIDTH = 0 ) ( input wire clk, input wire reset, @@ -23,7 +25,7 @@ module VX_cache_miss_resrv #( input wire[`BASE_ADDR_BITS-1:0] miss_add_wsel, input wire[`WORD_WIDTH-1:0] miss_add_data, input wire[`REQS_BITS-1:0] miss_add_tid, - input wire[CORE_TAG_WIDTH-1:0] miss_add_tag, + input wire[`REQ_TAG_WIDTH-1:0] miss_add_tag, input wire[`BYTE_EN_BITS-1:0] miss_add_mem_read, input wire[`BYTE_EN_BITS-1:0] miss_add_mem_write, input wire mrvq_init_ready_state, @@ -44,7 +46,7 @@ module VX_cache_miss_resrv #( output wire[`BASE_ADDR_BITS-1:0] miss_resrv_wsel_st0, output wire[`WORD_WIDTH-1:0] miss_resrv_data_st0, output wire[`REQS_BITS-1:0] miss_resrv_tid_st0, - output wire[CORE_TAG_WIDTH-1:0] miss_resrv_tag_st0, + output wire[`REQ_TAG_WIDTH-1:0] miss_resrv_tag_st0, output wire[`BYTE_EN_BITS-1:0] miss_resrv_mem_read_st0, output wire[`BYTE_EN_BITS-1:0] miss_resrv_mem_write_st0, output wire miss_resrv_is_snp_st0 diff --git a/hw/rtl/cache/VX_fill_invalidator.v b/hw/rtl/cache/VX_fill_invalidator.v index 563131e2..45fab1ca 100644 --- a/hw/rtl/cache/VX_fill_invalidator.v +++ b/hw/rtl/cache/VX_fill_invalidator.v @@ -20,7 +20,7 @@ module VX_fill_invalidator #( ); if (FILL_INVALIDAOR_SIZE == 0) begin - + assign invalidate_fill = 0; end else begin @@ -34,7 +34,8 @@ module VX_fill_invalidator #( integer i; always @(*) begin for (i = 0; i < FILL_INVALIDAOR_SIZE; i+=1) begin - matched_fill[i] = fills_active[i] && (fills_address[i] == fill_addr); + matched_fill[i] = fills_active[i] + && ((fills_address[i] == fill_addr) === 1); // use "case equality" to handle uninitialized entry end end @@ -55,8 +56,7 @@ module VX_fill_invalidator #( always @(posedge clk) begin if (reset) begin - fills_active <= 0; - fills_address <= 0; + fills_active <= 0; end else begin if (possible_fill && !matched && enqueue_found) begin fills_active [enqueue_index] <= 1; diff --git a/hw/rtl/cache/VX_snp_forwarder.v b/hw/rtl/cache/VX_snp_forwarder.v index 442e5008..da6c93aa 100644 --- a/hw/rtl/cache/VX_snp_forwarder.v +++ b/hw/rtl/cache/VX_snp_forwarder.v @@ -112,18 +112,18 @@ module VX_snp_forwarder #( assign snp_fwdin_ready[i] = fwdin_ready && (fwdin_sel == `REQS_BITS'(i)); end - /*always_comb begin + /*9always_comb begin if (1'($time & 1) && snp_req_valid && snp_req_ready) begin - $display("*** %t: ", $time); + $display("*** %t: snp req: addr=%0h, tag=%0h", $time, snp_req_addr, snp_req_tag); end - if (1'($time & 1) && snp_fwdout_valid && snp_fwdout_ready) begin - $display("*** %t: ", $time); + if (1'($time & 1) && snp_fwdout_valid[0] && snp_fwdout_ready[0]) begin + $display("*** %t: snp fwd_out: addr=%0h, tag=%0h", $time, snp_fwdout_addr[0], snp_fwdout_tag[0]); end if (1'($time & 1) && fwdin_valid && fwdin_ready) begin - $display("*** %t: ", $time); + $display("*** %t: snp fwd_in[%01d]: tag=%0h", $time, fwdin_sel, fwdin_tag); end if (1'($time & 1) && snp_rsp_valid && snp_rsp_ready) begin - $display("*** %t: ", $time); + $display("*** %t: snp rsp: addr=%0h, tag=%0h", $time, snp_rsp_addr, snp_rsp_tag); end end*/ diff --git a/simX/test_benchmark.sh b/simX/test_benchmark.sh index c3b09995..95315e98 100755 --- a/simX/test_benchmark.sh +++ b/simX/test_benchmark.sh @@ -1,3 +1,5 @@ +#!/bin/bash + echo start > results.txt make diff --git a/simX/test_riscv.sh b/simX/test_riscv.sh index 89e79497..8a158252 100755 --- a/simX/test_riscv.sh +++ b/simX/test_riscv.sh @@ -1,3 +1,5 @@ +#!/bin/bash + make cd obj_dir echo start > results.txt diff --git a/simX/test_runtime.sh b/simX/test_runtime.sh index 351f98f9..980da7d6 100755 --- a/simX/test_runtime.sh +++ b/simX/test_runtime.sh @@ -1,3 +1,5 @@ +#!/bin/bash + make make -C ../runtime/tests/dev make -C ../runtime/tests/hello diff --git a/simX/test_vec.sh b/simX/test_vec.sh index db6a9cf4..5be27e5f 100755 --- a/simX/test_vec.sh +++ b/simX/test_vec.sh @@ -1,3 +1,5 @@ +#!/bin/bash + echo start > results.txt # echo ../kernel/vortex_test.hex