Merge branch 'master' of https://github.gatech.edu/casl/Vortex

hw/rtl/VX_lsu_unit.v

@@ -113,7 +113,7 @@ module VX_lsu_unit #(
         end    
         if (mrq_pop_part) begin
             mem_rsp_mask[mrq_read_addr] <= mem_rsp_mask_upd;
-            assert(mrq_read_addr == dbg_mrq_write_addr);
+            assert(mrq_read_addr == dbg_mrq_write_addr);            
         end
     end
 

hw/rtl/cache/VX_bank.v

@@ -104,6 +104,7 @@ module VX_bank #(
 );
 
 `ifdef DBG_CORE_REQ_INFO
+    /* verilator lint_off UNUSED */
     wire[31:0]           debug_use_pc_st0;
     wire[1:0]            debug_wb_st0;
     wire[4:0]            debug_rd_st0;
@@ -130,6 +131,7 @@ module VX_bank #(
     wire[WORD_SIZE-1:0]  debug_byteen_st2;
     wire[`REQS_BITS-1:0] debug_tid_st2;
     wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st2;
+    /* verilator lint_on UNUSED */
 `endif
 
     wire snrq_pop;

hw/rtl/cache/VX_cache.v

@@ -128,11 +128,13 @@ module VX_cache #(
 );
 
 `ifdef DBG_CORE_REQ_INFO
+    /* verilator lint_off UNUSED */
     wire[31:0]           debug_core_req_use_pc;
     wire[1:0]            debug_core_req_wb;    
     wire[4:0]            debug_core_req_rd;
     wire[`NW_BITS-1:0]   debug_core_req_warp_num;
     wire[`LOG2UP(CREQ_SIZE)-1:0] debug_core_req_idx;
+    /* verilator lint_on UNUSED */
 
     if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
         assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rd, debug_core_req_warp_num, debug_core_req_idx} = core_req_tag[0];

hw/simulate/Makefile

@@ -3,16 +3,17 @@
 MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
 
 # control RTL debug print states
-DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
-				  -DDBG_PRINT_CORE_DCACHE \
-			      -DDBG_PRINT_CACHE_BANK  \
-				  -DDBG_PRINT_CACHE_SNP   \
-				  -DDBG_PRINT_CACHE_MSRQ  \
-				  -DDBG_PRINT_DRAM        \
-				  -DDBG_PRINT_PIPELINE    \
-				  -DDBG_PRINT_OPAE
+DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE
+DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE
+DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK 
+DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_SNP 
+DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSRQ
+DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM      
+DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE  
+DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
 
-#DBG_PRINT=$(DBG_PRINT_FLAGS)
+DBG_FLAGS += $(DBG_PRINT_FLAGS)
+DBG_FLAGS += -DDBG_CORE_REQ_INFO
 
 INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/pipe_regs -I../rtl/cache -I../rtl/simulate
 
@@ -27,7 +28,7 @@ VF += -Wno-DECLFILENAME
 VF += --x-initial unique
 VF += -exe $(SRCS) $(INCLUDE)
 
-DBG += -DVCD_OUTPUT $(DBG_PRINT)
+DBG += -DVCD_OUTPUT $(DBG_FLAGS)
 DBG += -DDBG_CORE_REQ_INFO
 
 THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')

hw/simulate/simulator.cpp

@@ -10,8 +10,12 @@ double sc_time_stamp() {
 }
 
 Simulator::Simulator() {    
+
+#ifdef NDEBUG
   // force random values for unitialized signals  
   Verilated::randReset(2);
+  Verilated::assertOn(false);
+#endif
 
   ram_ = nullptr;
   vortex_ = new VVortex();

hw/simulate/testbench.cpp

@@ -84,7 +84,7 @@ int main(int argc, char **argv)
 
 #else
 
-	char test[] = "../../../runtime/tests/simple/vx_simple_main.hex";
+	char test[] = "../../../runtime/tests/simple/vx_simple.hex";
 	//char test[] = "../../../benchmarks/riscv_tests/rv32ui-p-lb.hex";
 	//char test[] = "../../../benchmarks/riscv_tests/rv32ui-p-lw.hex";
 	//char test[] = "../../../benchmarks/riscv_tests/rv32ui-p-sw.hex";