diff --git a/hw/rtl/VX_gpu_unit.v b/hw/rtl/VX_gpu_unit.v
index f20232d7..f1d39ebc 100644
--- a/hw/rtl/VX_gpu_unit.v
+++ b/hw/rtl/VX_gpu_unit.v
@@ -102,8 +102,8 @@ module VX_gpu_unit #(
 
     `UNUSED_VAR (gpu_req_if.op_mod)
     
-    VX_tex_req_if   tex_req_if;
-    VX_tex_rsp_if   tex_rsp_if;    
+    VX_tex_req_if   tex_req_if();
+    VX_tex_rsp_if   tex_rsp_if();    
 
     wire is_tex = (gpu_req_if.op_type == `GPU_TEX);
 
diff --git a/hw/rtl/tex_unit/VX_tex_format.v b/hw/rtl/tex_unit/VX_tex_format.v
index 33cb4d24..b8168822 100644
--- a/hw/rtl/tex_unit/VX_tex_format.v
+++ b/hw/rtl/tex_unit/VX_tex_format.v
@@ -43,7 +43,8 @@ module VX_tex_format #(
             texel_out_r[23:16] = `TEX_COLOR_BITS'(texel_in[7:0]);
             texel_out_r[31:24] = {`TEX_COLOR_BITS{1'b1}};
         end
-        default: begin // `TEX_FORMAT_R8G8B8A8:
+        // `TEX_FORMAT_R8G8B8A8
+        default: begin 
             texel_out_r[07:00] = `TEX_COLOR_BITS'(texel_in[7:0]);
             texel_out_r[15:08] = `TEX_COLOR_BITS'(texel_in[15:8]);
             texel_out_r[23:16] = `TEX_COLOR_BITS'(texel_in[23:16]);
diff --git a/hw/rtl/tex_unit/VX_tex_lsu_arb.v b/hw/rtl/tex_unit/VX_tex_lsu_arb.v
index d35af222..04e742e8 100644
--- a/hw/rtl/tex_unit/VX_tex_lsu_arb.v
+++ b/hw/rtl/tex_unit/VX_tex_lsu_arb.v
@@ -1,4 +1,4 @@
-`include "VX_define.vh"
+`include "../cache/VX_cache_define.vh"
 
 module VX_tex_lsu_arb #(    
     parameter NUM_REQS      = 1, 
diff --git a/hw/syn/quartus/pipeline/Makefile b/hw/syn/quartus/pipeline/Makefile
index 095e19ce..84b5889f 100644
--- a/hw/syn/quartus/pipeline/Makefile
+++ b/hw/syn/quartus/pipeline/Makefile
@@ -1,8 +1,16 @@
-PROJECT = VX_pipeline
-TOP_LEVEL_ENTITY = VX_pipeline
-SRC_FILE = VX_pipeline.v
-FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera/arria10;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src
-RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces
+# Part, Family
+FAMILY = "Arria 10"
+DEVICE = 10AX115N3F40E2SG 
+
+PROJECT = Core
+TOP_LEVEL_ENTITY = VX_core
+SRC_FILE = VX_core.v
+
+RTL_DIR=../../../rtl
+FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(RTL_DIR)/fp_cores/altera/arria10;$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
+TEX_INCLUDE = $(RTL_DIR)/tex_unit
+RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE)
+
 PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
 
 # Part, Family