rebase master update
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Blaise Tine
151
hw/rtl/tex_unit/VX_tex_addr.v
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151
hw/rtl/tex_unit/VX_tex_addr.v
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`include "VX_tex_define.vh"
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module VX_tex_addr #(
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parameter CORE_ID = 0,
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parameter REQ_INFO_WIDTH = 1,
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parameter NUM_REQS = 1
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) (
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input wire clk,
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input wire reset,
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// inputs
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input wire req_valid,
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input wire [NUM_REQS-1:0] req_tmask,
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input wire [1:0][NUM_REQS-1:0][31:0] req_coords,
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input wire [`TEX_FORMAT_BITS-1:0] req_format,
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input wire [`TEX_FILTER_BITS-1:0] req_filter,
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input wire [1:0][`TEX_WRAP_BITS-1:0] req_wraps,
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input wire [`TEX_ADDR_BITS-1:0] req_baseaddr,
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input wire [NUM_REQS-1:0][`TEX_MIPOFF_BITS-1:0] req_mipoffset,
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input wire [1:0][NUM_REQS-1:0][`TEX_DIM_BITS-1:0] req_logdims,
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input wire [REQ_INFO_WIDTH-1:0] req_info,
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output wire req_ready,
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// outputs
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output wire rsp_valid,
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output wire [NUM_REQS-1:0] rsp_tmask,
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output wire [`TEX_FILTER_BITS-1:0] rsp_filter,
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output wire [`TEX_STRIDE_BITS-1:0] rsp_stride,
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output wire [NUM_REQS-1:0][3:0][31:0] rsp_addr,
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output wire [1:0][NUM_REQS-1:0][`BLEND_FRAC-1:0] rsp_blends,
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output wire [REQ_INFO_WIDTH-1:0] rsp_info,
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input wire rsp_ready
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);
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`UNUSED_PARAM (CORE_ID)
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wire valid_s0;
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wire [NUM_REQS-1:0] tmask_s0;
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wire [`TEX_FILTER_BITS-1:0] filter_s0;
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wire [REQ_INFO_WIDTH-1:0] req_info_s0;
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wire [1:0][NUM_REQS-1:0][`FIXED_FRAC-1:0] clamped_lo, clamped_lo_s0;
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wire [1:0][NUM_REQS-1:0][`FIXED_FRAC-1:0] clamped_hi, clamped_hi_s0;
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wire [`TEX_STRIDE_BITS-1:0] log_stride, log_stride_s0;
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wire [NUM_REQS-1:0][31:0] mip_addr, mip_addr_s0;
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wire [1:0][NUM_REQS-1:0][`TEX_DIM_BITS-1:0] log_dims_s0;
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wire stall_out;
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// stride
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VX_tex_stride #(
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.CORE_ID (CORE_ID)
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) tex_stride (
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.format (req_format),
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.log_stride (log_stride)
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);
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// addressing mode
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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for (genvar j = 0; j < 2; ++j) begin
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wire [31:0] coord_lo, coord_hi;
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assign coord_lo = req_coords[j][i] - (req_filter ? (`FIXED_HALF >> req_logdims[j][i]) : 0);
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assign coord_hi = req_coords[j][i] + (req_filter ? (`FIXED_HALF >> req_logdims[j][i]) : 0);
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VX_tex_wrap #(
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.CORE_ID (CORE_ID)
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) tex_wrap_lo (
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.wrap_i (req_wraps[j]),
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.coord_i (coord_lo),
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.coord_o (clamped_lo[j][i])
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);
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VX_tex_wrap #(
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.CORE_ID (CORE_ID)
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) tex_wrap_hi (
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.wrap_i (req_wraps[j]),
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.coord_i (coord_hi),
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.coord_o (clamped_hi[j][i])
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);
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end
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assign mip_addr[i] = req_baseaddr + 32'(req_mipoffset[i]);
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end
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VX_pipe_register #(
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.DATAW (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFO_WIDTH + NUM_REQS * (2 * `TEX_DIM_BITS + 32 + 2 * 2 * `FIXED_FRAC)),
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.RESETW (1)
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) pipe_reg0 (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({req_valid, req_tmask, req_filter, log_stride, req_info, req_logdims, mip_addr, clamped_lo, clamped_hi}),
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.data_out ({valid_s0, tmask_s0, filter_s0, log_stride_s0, req_info_s0, log_dims_s0, mip_addr_s0, clamped_lo_s0, clamped_hi_s0})
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);
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// addresses generation
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wire [1:0][NUM_REQS-1:0][`FIXED_INT-1:0] scaled_lo, scaled_hi;
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wire [1:0][NUM_REQS-1:0][`BLEND_FRAC-1:0] blends;
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wire [NUM_REQS-1:0][3:0][31:0] addr;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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for (genvar j = 0; j < 2; ++j) begin
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assign scaled_lo[j][i] = `FIXED_INT'(clamped_lo_s0[j][i] >> ((`FIXED_FRAC) - log_dims_s0[j][i]));
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assign scaled_hi[j][i] = `FIXED_INT'(clamped_hi_s0[j][i] >> ((`FIXED_FRAC) - log_dims_s0[j][i]));
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assign blends[j][i] = filter_s0 ? clamped_lo_s0[j][i][`BLEND_FRAC-1:0] : `BLEND_FRAC'(0);
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end
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end
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign addr[i][0] = mip_addr_s0[i] + (32'(scaled_lo[0][i]) + (32'(scaled_lo[1][i]) << log_dims_s0[0][i])) << log_stride_s0;
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assign addr[i][1] = mip_addr_s0[i] + (32'(scaled_hi[0][i]) + (32'(scaled_lo[1][i]) << log_dims_s0[0][i])) << log_stride_s0;
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assign addr[i][2] = mip_addr_s0[i] + (32'(scaled_lo[0][i]) + (32'(scaled_hi[1][i]) << log_dims_s0[0][i])) << log_stride_s0;
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assign addr[i][3] = mip_addr_s0[i] + (32'(scaled_hi[0][i]) + (32'(scaled_hi[1][i]) << log_dims_s0[0][i])) << log_stride_s0;
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end
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assign stall_out = rsp_valid && ~rsp_ready;
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VX_pipe_register #(
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.DATAW (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (NUM_REQS * 4 * 32) + (2 * NUM_REQS * `BLEND_FRAC) + REQ_INFO_WIDTH),
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.RESETW (1)
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) pipe_reg1 (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({valid_s0, tmask_s0, filter_s0, log_stride_s0, addr, blends, req_info_s0}),
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.data_out ({rsp_valid, rsp_tmask, rsp_filter, rsp_stride, rsp_addr, rsp_blends, rsp_info})
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);
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assign req_ready = ~stall_out;
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`ifdef DBG_PRINT_TEX
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wire [`NW_BITS-1:0] rsp_wid;
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wire [31:0] rsp_PC;
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assign {rsp_wid, rsp_PC} = rsp_info[`NW_BITS+32-1:0];
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always @(posedge clk) begin
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if (rsp_valid && rsp_ready) begin
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$write("%t: core%0d-tex-addr: wid=%0d, PC=%0h, tmask=%b, req_filter=%0d, tride=%0d, addr=",
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$time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask, rsp_filter, rsp_stride);
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`PRINT_ARRAY2D(rsp_addr, 4, NUM_REQS);
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$write("\n");
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end
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end
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`endif
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endmodule
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