rebase master update

hw/rtl/interfaces/VX_cmt_to_csr_if.v

@@ -3,10 +3,12 @@
 
 `include "VX_define.vh"
 
-interface VX_cmt_to_csr_if ();
+interface VX_cmt_to_csr_if #(
+    parameter SIZE
+)();
 
-    wire                                valid;
-    wire [$clog2(3*`NUM_THREADS+1)-1:0] commit_size;
+    wire            valid;
+    wire [SIZE-1:0] commit_size;
 
 endinterface
 

hw/rtl/interfaces/VX_gpu_req_if.v

@@ -12,8 +12,10 @@ interface VX_gpu_req_if();
     wire [31:0]             PC;
     wire [31:0]             next_PC;
     wire [`GPU_BITS-1:0]    op_type;
+    wire [`MOD_BITS-1:0]    op_mod;
     wire [`NUM_THREADS-1:0][31:0] rs1_data;
-    wire [31:0]             rs2_data;
+    wire [`NUM_THREADS-1:0][31:0] rs2_data;
+    wire [`NUM_THREADS-1:0][31:0] rs3_data;
     wire [`NR_BITS-1:0]     rd;
     wire                    wb;
     

hw/rtl/interfaces/VX_tex_csr_if.v

@@ -0,0 +1,14 @@
+`ifndef VX_TEX_CSR_IF
+`define VX_TEX_CSR_IF
+
+`include "VX_define.vh"
+
+interface VX_tex_csr_if ();
+
+    wire                      write_enable; 
+    wire [`CSR_ADDR_BITS-1:0] write_addr;
+    wire [31:0]               write_data;   
+
+endinterface
+
+`endif

hw/rtl/interfaces/VX_tex_req_if.v

@@ -0,0 +1,25 @@
+`ifndef VX_TEX_REQ_IF
+`define VX_TEX_REQ_IF
+
+`include "VX_define.vh"
+
+interface VX_tex_req_if ();
+
+    wire                            valid;      
+    wire [`NW_BITS-1:0]             wid;
+    wire [`NUM_THREADS-1:0]         tmask;    
+    wire [31:0]                     PC;    
+    wire [`NR_BITS-1:0]             rd;    
+    wire                            wb;
+
+    wire [`NTEX_BITS-1:0]           unit;
+    wire [1:0][`NUM_THREADS-1:0][31:0] coords;
+    wire [`NUM_THREADS-1:0][31:0]   lod;
+    
+    wire                            ready;
+
+endinterface
+`endif
+
+
+ 

hw/rtl/interfaces/VX_tex_rsp_if.v

@@ -0,0 +1,21 @@
+`ifndef VX_TEX_RSP_IF
+`define VX_TEX_RSP_IF
+
+`include "VX_define.vh"
+
+interface VX_tex_rsp_if ();
+
+    wire                    valid;   
+    wire [`NW_BITS-1:0]     wid;
+    wire [`NUM_THREADS-1:0] tmask;    
+    wire [31:0]             PC;    
+    wire [`NR_BITS-1:0]     rd;
+    wire                    wb;
+    wire [`NUM_THREADS-1:0][31:0] data;
+    wire                    ready;
+
+endinterface
+
+`endif
+ 
+