Added Split/Join - not tested

rtl/VX_generic_stack.v

@@ -5,11 +5,11 @@ module VX_generic_stack
 	)
 	(
 	input  wire              clk,
-	input  wire              reset,
 	input  wire              push,
 	input  wire              pop,
-	input  wire[WIDTH - 1:0] d,
-	output reg [WIDTH - 1:0] q,
+	input  reg [WIDTH - 1:0] q1,
+	input  reg [WIDTH - 1:0] q2,
+	output wire[WIDTH - 1:0] d
 	);
 
 
@@ -17,24 +17,22 @@ module VX_generic_stack
 	reg [WIDTH - 1:0] stack [0:(1 << DEPTH) - 1];
 
 	always @(posedge clk) begin
-		if (reset)
-			ptr <= 0;
-		else if (push)
-			ptr <= ptr + 1;
+		// if (reset)
+		// 	ptr <= 0;
+		// else 
+		if (push)
+			ptr <= ptr + 2;
 		else if (pop)
 			ptr <= ptr - 1;
 	end
 
 	always @(posedge clk) begin
 		if (push) begin
-			if(push)
-				stack[ptr] <= q;
+			stack[ptr]   <= q1;
+			stack[ptr+1] <= q2;
 		end
 	end
 
-	always @(*) begin
-		if (pop)
-			q <= stack[ptr - 1];
-	end
+	assign d = stack[ptr - 1];
 
 endmodule