cache refactoring - phase 2

2020-11-03 04:51:40 -08:00
parent 5be1d85648
commit ba81d76e02
19 changed files with 567 additions and 424 deletions
--- a/hw/rtl/libs/VX_dp_ram.v
+++ b/hw/rtl/libs/VX_dp_ram.v
@@ -73,7 +73,7 @@ module VX_dp_ram #(

    end else begin

-        `UNUSED_VAR(rden)
+        `UNUSED_VAR (rden)

        if (RWCHECK) begin