Move the memory models from Cache_Progress to Master branch
This commit is contained in:
Lingjun Zhu
33
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.bitmap
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33
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.bitmap
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File diff suppressed because one or more lines are too long
69
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.cpf
Normal file
69
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.cpf
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File diff suppressed because one or more lines are too long
1306
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.ctl
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1306
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.ctl
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File diff suppressed because it is too large
Load Diff
31693
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.lef
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31693
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.lef
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File diff suppressed because it is too large
Load Diff
2703
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.mdt
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2703
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.mdt
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File diff suppressed because it is too large
Load Diff
358
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.memlib
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358
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.memlib
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@@ -0,0 +1,358 @@
|
|||||||
|
/* logicvision_memcomp Version: c0.1.5-EAC */
|
||||||
|
/* common_memcomp Version: c0.1.2-EAC */
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||||||
|
/* lang compiler Version: 4.5.1-EAC Nov 6 2014 16:10:45 */
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||||||
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//
|
||||||
|
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||||
|
//
|
||||||
|
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||||
|
//
|
||||||
|
// Use of this Software is subject to the terms and conditions of the
|
||||||
|
// applicable license agreement with ARM Physical IP, Inc.
|
||||||
|
// In addition, this Software is protected by patents, copyright law
|
||||||
|
// and international treaties.
|
||||||
|
//
|
||||||
|
// The copyright notice(s) in this Software does not indicate actual or
|
||||||
|
// intended publication of this Software.
|
||||||
|
//
|
||||||
|
// logicvision model for High Capacity Two Port Register File SVT MVT Compiler
|
||||||
|
//
|
||||||
|
// Instance Name: rf2_32x128_wm1
|
||||||
|
// Words: 32
|
||||||
|
// Bits: 128
|
||||||
|
// Mux: 2
|
||||||
|
// Drive: 6
|
||||||
|
// Write Mask: On
|
||||||
|
// Extra Margin Adjustment: On
|
||||||
|
// Redundant Rows: 0
|
||||||
|
// Redundant Columns: 2
|
||||||
|
// Test Muxes On
|
||||||
|
//
|
||||||
|
// Creation Date: Sun Oct 13 11:08:56 2019
|
||||||
|
// Version: r0p0
|
||||||
|
//
|
||||||
|
// Modeling Assumptions:
|
||||||
|
//
|
||||||
|
// Modeling Limitations: None
|
||||||
|
//
|
||||||
|
// Known Bugs: None.
|
||||||
|
//
|
||||||
|
// Known Work Arounds: N/A
|
||||||
|
//
|
||||||
|
MemoryTemplate (rf2_32x128_wm1) {
|
||||||
|
Algorithm : SmarchChkbvcd;
|
||||||
|
DataOutStage : None;
|
||||||
|
LogicalPorts : 1R1W;
|
||||||
|
BitGrouping : 1;
|
||||||
|
MemoryType : SRAM;
|
||||||
|
MinHold : 0.5;
|
||||||
|
OperationSet : SyncWRvcd;
|
||||||
|
SelectDuringWriteThru : Off;
|
||||||
|
ShadowRead : On;
|
||||||
|
ShadowWrite : On;
|
||||||
|
ShadowWriteOk : On;
|
||||||
|
TransparentMode : None;
|
||||||
|
ObservationLogic: On;
|
||||||
|
InternalScanLogic: On;
|
||||||
|
CellName : rf2_32x128_wm1;
|
||||||
|
NumberOfWords : 32;
|
||||||
|
AddressCounter{
|
||||||
|
Function (Address) {
|
||||||
|
LogicalAddressMap{
|
||||||
|
ColumnAddress[0] : Address[0];
|
||||||
|
RowAddress[3:0] : Address[4:1];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
Function (ColumnAddress) {
|
||||||
|
CountRange [0:1];
|
||||||
|
}
|
||||||
|
Function (RowAddress) {
|
||||||
|
CountRange [0:15];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
PhysicalAddressMap{
|
||||||
|
ColumnAddress[0] : c[0];
|
||||||
|
RowAddress[0] : r[0];
|
||||||
|
RowAddress[1] : r[1];
|
||||||
|
RowAddress[2] : r[2];
|
||||||
|
RowAddress[3] : r[3];
|
||||||
|
}
|
||||||
|
PhysicalDataMap{
|
||||||
|
Data[0] : NOT d[0];
|
||||||
|
Data[1] : NOT d[1];
|
||||||
|
Data[2] : NOT d[2];
|
||||||
|
Data[3] : NOT d[3];
|
||||||
|
Data[4] : NOT d[4];
|
||||||
|
Data[5] : NOT d[5];
|
||||||
|
Data[6] : NOT d[6];
|
||||||
|
Data[7] : NOT d[7];
|
||||||
|
Data[8] : NOT d[8];
|
||||||
|
Data[9] : NOT d[9];
|
||||||
|
Data[10] : NOT d[10];
|
||||||
|
Data[11] : NOT d[11];
|
||||||
|
Data[12] : NOT d[12];
|
||||||
|
Data[13] : NOT d[13];
|
||||||
|
Data[14] : NOT d[14];
|
||||||
|
Data[15] : NOT d[15];
|
||||||
|
Data[16] : NOT d[16];
|
||||||
|
Data[17] : NOT d[17];
|
||||||
|
Data[18] : NOT d[18];
|
||||||
|
Data[19] : NOT d[19];
|
||||||
|
Data[20] : NOT d[20];
|
||||||
|
Data[21] : NOT d[21];
|
||||||
|
Data[22] : NOT d[22];
|
||||||
|
Data[23] : NOT d[23];
|
||||||
|
Data[24] : NOT d[24];
|
||||||
|
Data[25] : NOT d[25];
|
||||||
|
Data[26] : NOT d[26];
|
||||||
|
Data[27] : NOT d[27];
|
||||||
|
Data[28] : NOT d[28];
|
||||||
|
Data[29] : NOT d[29];
|
||||||
|
Data[30] : NOT d[30];
|
||||||
|
Data[31] : NOT d[31];
|
||||||
|
Data[32] : NOT d[32];
|
||||||
|
Data[33] : NOT d[33];
|
||||||
|
Data[34] : NOT d[34];
|
||||||
|
Data[35] : NOT d[35];
|
||||||
|
Data[36] : NOT d[36];
|
||||||
|
Data[37] : NOT d[37];
|
||||||
|
Data[38] : NOT d[38];
|
||||||
|
Data[39] : NOT d[39];
|
||||||
|
Data[40] : NOT d[40];
|
||||||
|
Data[41] : NOT d[41];
|
||||||
|
Data[42] : NOT d[42];
|
||||||
|
Data[43] : NOT d[43];
|
||||||
|
Data[44] : NOT d[44];
|
||||||
|
Data[45] : NOT d[45];
|
||||||
|
Data[46] : NOT d[46];
|
||||||
|
Data[47] : NOT d[47];
|
||||||
|
Data[48] : NOT d[48];
|
||||||
|
Data[49] : NOT d[49];
|
||||||
|
Data[50] : NOT d[50];
|
||||||
|
Data[51] : NOT d[51];
|
||||||
|
Data[52] : NOT d[52];
|
||||||
|
Data[53] : NOT d[53];
|
||||||
|
Data[54] : NOT d[54];
|
||||||
|
Data[55] : NOT d[55];
|
||||||
|
Data[56] : NOT d[56];
|
||||||
|
Data[57] : NOT d[57];
|
||||||
|
Data[58] : NOT d[58];
|
||||||
|
Data[59] : NOT d[59];
|
||||||
|
Data[60] : NOT d[60];
|
||||||
|
Data[61] : NOT d[61];
|
||||||
|
Data[62] : NOT d[62];
|
||||||
|
Data[63] : NOT d[63];
|
||||||
|
Data[64] : d[64];
|
||||||
|
Data[65] : d[65];
|
||||||
|
Data[66] : d[66];
|
||||||
|
Data[67] : d[67];
|
||||||
|
Data[68] : d[68];
|
||||||
|
Data[69] : d[69];
|
||||||
|
Data[70] : d[70];
|
||||||
|
Data[71] : d[71];
|
||||||
|
Data[72] : d[72];
|
||||||
|
Data[73] : d[73];
|
||||||
|
Data[74] : d[74];
|
||||||
|
Data[75] : d[75];
|
||||||
|
Data[76] : d[76];
|
||||||
|
Data[77] : d[77];
|
||||||
|
Data[78] : d[78];
|
||||||
|
Data[79] : d[79];
|
||||||
|
Data[80] : d[80];
|
||||||
|
Data[81] : d[81];
|
||||||
|
Data[82] : d[82];
|
||||||
|
Data[83] : d[83];
|
||||||
|
Data[84] : d[84];
|
||||||
|
Data[85] : d[85];
|
||||||
|
Data[86] : d[86];
|
||||||
|
Data[87] : d[87];
|
||||||
|
Data[88] : d[88];
|
||||||
|
Data[89] : d[89];
|
||||||
|
Data[90] : d[90];
|
||||||
|
Data[91] : d[91];
|
||||||
|
Data[92] : d[92];
|
||||||
|
Data[93] : d[93];
|
||||||
|
Data[94] : d[94];
|
||||||
|
Data[95] : d[95];
|
||||||
|
Data[96] : d[96];
|
||||||
|
Data[97] : d[97];
|
||||||
|
Data[98] : d[98];
|
||||||
|
Data[99] : d[99];
|
||||||
|
Data[100] : d[100];
|
||||||
|
Data[101] : d[101];
|
||||||
|
Data[102] : d[102];
|
||||||
|
Data[103] : d[103];
|
||||||
|
Data[104] : d[104];
|
||||||
|
Data[105] : d[105];
|
||||||
|
Data[106] : d[106];
|
||||||
|
Data[107] : d[107];
|
||||||
|
Data[108] : d[108];
|
||||||
|
Data[109] : d[109];
|
||||||
|
Data[110] : d[110];
|
||||||
|
Data[111] : d[111];
|
||||||
|
Data[112] : d[112];
|
||||||
|
Data[113] : d[113];
|
||||||
|
Data[114] : d[114];
|
||||||
|
Data[115] : d[115];
|
||||||
|
Data[116] : d[116];
|
||||||
|
Data[117] : d[117];
|
||||||
|
Data[118] : d[118];
|
||||||
|
Data[119] : d[119];
|
||||||
|
Data[120] : d[120];
|
||||||
|
Data[121] : d[121];
|
||||||
|
Data[122] : d[122];
|
||||||
|
Data[123] : d[123];
|
||||||
|
Data[124] : d[124];
|
||||||
|
Data[125] : d[125];
|
||||||
|
Data[126] : d[126];
|
||||||
|
Data[127] : d[127];
|
||||||
|
}
|
||||||
|
Port (AA[4:0]) {
|
||||||
|
Function : Address;
|
||||||
|
LogicalPort : A;
|
||||||
|
EmbeddedTestLogic {
|
||||||
|
TestInput : TAA[4:0];
|
||||||
|
TestOutput : AYA[4:0];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
Port (QA[127:0]) {
|
||||||
|
Function : Data;
|
||||||
|
Direction : output;
|
||||||
|
LogicalPort : A;
|
||||||
|
}
|
||||||
|
Port (CENA) {
|
||||||
|
Function : ReadEnable;
|
||||||
|
LogicalPort : A;
|
||||||
|
Polarity : ActiveLow;
|
||||||
|
EmbeddedTestLogic {
|
||||||
|
TestInput : TCENA;
|
||||||
|
TestOutput : CENYA;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
Port (TENA) {
|
||||||
|
Function : BISTOn;
|
||||||
|
Direction : Input;
|
||||||
|
LogicalPort : A;
|
||||||
|
Polarity : ActiveLow;
|
||||||
|
}
|
||||||
|
Port (CLKA) {
|
||||||
|
Function : Clock;
|
||||||
|
LogicalPort : A;
|
||||||
|
Polarity : ActiveHigh;
|
||||||
|
}
|
||||||
|
Port (EMAA[2:0]) {
|
||||||
|
Function : None;
|
||||||
|
SafeValue : 0;
|
||||||
|
Direction : Input;
|
||||||
|
LogicalPort : A;
|
||||||
|
Polarity : ActiveHigh;
|
||||||
|
}
|
||||||
|
Port (EMASA) {
|
||||||
|
Function : None;
|
||||||
|
SafeValue : 0;
|
||||||
|
Direction : Input;
|
||||||
|
LogicalPort : A;
|
||||||
|
Polarity : ActiveHigh;
|
||||||
|
}
|
||||||
|
port (SEA){
|
||||||
|
Function : None;
|
||||||
|
Direction : Input;
|
||||||
|
SafeValue : 0;
|
||||||
|
Polarity : ActiveHigh;
|
||||||
|
}
|
||||||
|
port (SIA[1:0]){
|
||||||
|
Function : None;
|
||||||
|
Direction : Input;
|
||||||
|
SafeValue : 0;
|
||||||
|
Polarity : ActiveHigh;
|
||||||
|
}
|
||||||
|
port (SOA[1:0]){
|
||||||
|
Function : None;
|
||||||
|
Direction : Output;
|
||||||
|
}
|
||||||
|
port (DFTRAMBYP){
|
||||||
|
Function : ScanTest;
|
||||||
|
Direction : Input;
|
||||||
|
Polarity : ActiveHigh;
|
||||||
|
}
|
||||||
|
Port (AB[4:0]) {
|
||||||
|
Function : Address;
|
||||||
|
LogicalPort : B;
|
||||||
|
EmbeddedTestLogic {
|
||||||
|
TestInput : TAB[4:0];
|
||||||
|
TestOutput : AYB[4:0];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
Port (DB[127:0]) {
|
||||||
|
Function : Data;
|
||||||
|
Direction : input;
|
||||||
|
LogicalPort : B;
|
||||||
|
EmbeddedTestLogic {
|
||||||
|
TestInput : TDB[127:0];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
Port (WENB[127:0]) {
|
||||||
|
Function : GroupWriteEnable;
|
||||||
|
BitsPerWriteEnable: 1;
|
||||||
|
LogicalPort : B;
|
||||||
|
Polarity : ActiveLow;
|
||||||
|
EmbeddedTestLogic {
|
||||||
|
TestInput : TWENB[127:0];
|
||||||
|
TestOutput : WENYB[127:0];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
Port (CENB) {
|
||||||
|
Function : WriteEnable;
|
||||||
|
LogicalPort : B;
|
||||||
|
Polarity : ActiveLow;
|
||||||
|
EmbeddedTestLogic {
|
||||||
|
TestInput : TCENB;
|
||||||
|
TestOutput : CENYB;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
Port (TENB) {
|
||||||
|
Function : BISTOn;
|
||||||
|
Direction : Input;
|
||||||
|
LogicalPort : B;
|
||||||
|
Polarity : ActiveLow;
|
||||||
|
}
|
||||||
|
Port (CLKB) {
|
||||||
|
Function : Clock;
|
||||||
|
LogicalPort : B;
|
||||||
|
Polarity : ActiveHigh;
|
||||||
|
}
|
||||||
|
Port (EMAB[2:0]) {
|
||||||
|
Function : None;
|
||||||
|
SafeValue : 0;
|
||||||
|
Direction : Input;
|
||||||
|
LogicalPort : B;
|
||||||
|
Polarity : ActiveHigh;
|
||||||
|
}
|
||||||
|
Port (COLLDISN) {
|
||||||
|
Function : None;
|
||||||
|
SafeValue : 1;
|
||||||
|
Direction : Input;
|
||||||
|
Polarity : ActiveLow;
|
||||||
|
}
|
||||||
|
port (SEB){
|
||||||
|
Function : None;
|
||||||
|
Direction : Input;
|
||||||
|
SafeValue : 0;
|
||||||
|
Polarity : ActiveHigh;
|
||||||
|
}
|
||||||
|
port (SIB[1:0]){
|
||||||
|
Function : None;
|
||||||
|
Direction : Input;
|
||||||
|
SafeValue : 0;
|
||||||
|
Polarity : ActiveHigh;
|
||||||
|
}
|
||||||
|
port (SOB[1:0]){
|
||||||
|
Function : None;
|
||||||
|
Direction : Output;
|
||||||
|
}
|
||||||
|
port (RET1N){
|
||||||
|
Function : None;
|
||||||
|
Direction : Input;
|
||||||
|
SafeValue : 1;
|
||||||
|
Polarity : Activelow;
|
||||||
|
}
|
||||||
|
}
|
||||||
2410
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.tv
Normal file
2410
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.tv
Normal file
File diff suppressed because it is too large
Load Diff
15361
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
Normal file
15361
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
Normal file
File diff suppressed because it is too large
Load Diff
1121
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_antenna.clf
Normal file
1121
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_antenna.clf
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,162 @@
|
|||||||
|
#
|
||||||
|
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||||
|
#
|
||||||
|
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||||
|
#
|
||||||
|
# Use of this Software is subject to the terms and conditions of the
|
||||||
|
# applicable license agreement with ARM Physical IP, Inc.
|
||||||
|
# In addition, this Software is protected by patents, copyright law
|
||||||
|
# and international treaties.
|
||||||
|
#
|
||||||
|
# The copyright notice(s) in this Software does not indicate actual or
|
||||||
|
# intended publication of this Software.
|
||||||
|
#
|
||||||
|
# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
|
||||||
|
#
|
||||||
|
# Creation Date: Sun Oct 13 11:07:58 2019
|
||||||
|
#
|
||||||
|
# Instance Options:
|
||||||
|
# Instance Name: rf2_32x128_wm1
|
||||||
|
# Number of Words: 32
|
||||||
|
# Number of Bits: 128
|
||||||
|
# Multiplexer Width: 2
|
||||||
|
# Multi-Vt selection: LL
|
||||||
|
# Frequency <MHz>: 1
|
||||||
|
# Activity Factor <%>: 50
|
||||||
|
# Pipeline: off
|
||||||
|
# Word-Write Mask: on
|
||||||
|
# Word Partition Size: 1
|
||||||
|
# Write through: off
|
||||||
|
# Top Metal Layer: m5-m10
|
||||||
|
# Power Type: otc
|
||||||
|
# Redundancy: off
|
||||||
|
# Redundant Columns: 2
|
||||||
|
# Redundant Rows: 0
|
||||||
|
# BIST MUXes: on
|
||||||
|
# Soft Error Repair (SER): none
|
||||||
|
# Power Gating: off
|
||||||
|
# Back Biasing: off
|
||||||
|
# Retention: on
|
||||||
|
# Extra Margin Adjustment: on
|
||||||
|
# Advanced Test Features: off
|
||||||
|
# Customer Comment: This is a memory instance
|
||||||
|
# Bus-notation: on
|
||||||
|
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||||
|
# Name Case: upper
|
||||||
|
# Check Instance Name: on
|
||||||
|
# Diodes: on
|
||||||
|
# Drive Strength: 6
|
||||||
|
# Site Definitions: off
|
||||||
|
# Library Name: USERLIB
|
||||||
|
# Liberty setting: nldm
|
||||||
|
#
|
||||||
|
# Compiler Versions:
|
||||||
|
# Memory Version: r0p0
|
||||||
|
# Lang compiler Version: 4.5.1-EAC
|
||||||
|
# View Name: avm
|
||||||
|
# AMCI Version: 2.0.4-EAC
|
||||||
|
# avm_memcomp Version: 2.3.7-EAC
|
||||||
|
#
|
||||||
|
# Modeling Assumptions: N/A
|
||||||
|
#
|
||||||
|
# Modeling Limitations: N/A
|
||||||
|
#
|
||||||
|
# Known Bugs: N/A
|
||||||
|
#
|
||||||
|
# Known Work Arounds: N/A
|
||||||
|
#
|
||||||
|
rf2_32x128_wm1 {
|
||||||
|
MEMORY_TYPE RegFile
|
||||||
|
EQUIV_GATE_COUNT 4506
|
||||||
|
VDD_PIN VDDCE VDDPE
|
||||||
|
GND_PIN VSSE
|
||||||
|
#This file is for PROCESS FF, CORNER FF_0P99V_0P99V_M40C
|
||||||
|
#However, RedHawk needs the process to be specified as 'PROCESS XX'
|
||||||
|
PROCESS XX
|
||||||
|
Cload 3.5e-05nF
|
||||||
|
VDD 0.99 0.99
|
||||||
|
|
||||||
|
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
|
||||||
|
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
|
||||||
|
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||||
|
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
|
||||||
|
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||||
|
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
|
||||||
|
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
|
||||||
|
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
|
||||||
|
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
|
||||||
|
|
||||||
|
Cpd avm_into_lowpwr {
|
||||||
|
VDDCE VSSE 5.92707e-05nF
|
||||||
|
VDDPE VSSE 6.01330e-04nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_into_lowpwr {
|
||||||
|
VDDCE VSSE 2.06670mA
|
||||||
|
VDDPE VSSE 7.00670mA
|
||||||
|
}
|
||||||
|
Cpd avm_outof_lowpwr {
|
||||||
|
VDDCE VSSE 6.51978e-05nF
|
||||||
|
VDDPE VSSE 4.44480e-03nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_outof_lowpwr {
|
||||||
|
VDDCE VSSE 2.27337mA
|
||||||
|
VDDPE VSSE 40.32645mA
|
||||||
|
}
|
||||||
|
Cpd avm_read_write {
|
||||||
|
VDDCE VSSE 3.12285e-04nF
|
||||||
|
VDDPE VSSE 8.61142e-03nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_read_write {
|
||||||
|
VDDCE VSSE 5.75579mA
|
||||||
|
VDDPE VSSE 75.37331mA
|
||||||
|
}
|
||||||
|
Cpd avm_read_desel {
|
||||||
|
VDDCE VSSE 9.25793e-05nF
|
||||||
|
VDDPE VSSE 3.63286e-03nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_read_desel {
|
||||||
|
VDDCE VSSE 2.15420mA
|
||||||
|
VDDPE VSSE 42.96800mA
|
||||||
|
}
|
||||||
|
Cpd avm_desel_write {
|
||||||
|
VDDCE VSSE 2.19705e-04nF
|
||||||
|
VDDPE VSSE 4.97856e-03nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_desel_write {
|
||||||
|
VDDCE VSSE 4.56860mA
|
||||||
|
VDDPE VSSE 62.31700mA
|
||||||
|
}
|
||||||
|
Cpd avm_scan_capture {
|
||||||
|
VDDCE VSSE 8.97079e-06nF
|
||||||
|
VDDPE VSSE 1.11565e-02nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_scan_capture {
|
||||||
|
VDDCE VSSE 0.54208mA
|
||||||
|
VDDPE VSSE 46.13168mA
|
||||||
|
}
|
||||||
|
Cpd avm_scan_shift {
|
||||||
|
VDDCE VSSE 8.97079e-06nF
|
||||||
|
VDDPE VSSE 1.11565e-02nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_scan_shift {
|
||||||
|
VDDCE VSSE 0.54208mA
|
||||||
|
VDDPE VSSE 46.13168mA
|
||||||
|
}
|
||||||
|
Cpd standby_trig {
|
||||||
|
VDDCE VSSE 0.00000e+00nF
|
||||||
|
VDDPE VSSE 1.88451e-05nF
|
||||||
|
}
|
||||||
|
Cpd standby_ntrig {
|
||||||
|
VDDCE VSSE 0.00000e+00nF
|
||||||
|
VDDPE VSSE 4.76848e-05nF
|
||||||
|
}
|
||||||
|
LEAKAGE_I {
|
||||||
|
VDDCE VSSE 2.29200e-03mA
|
||||||
|
VDDPE VSSE 9.63200e-03mA
|
||||||
|
}
|
||||||
|
tsu 0.074586ns
|
||||||
|
ck2q_delay 0.386174ns
|
||||||
|
tr_q 0.012874ns
|
||||||
|
tf_q 0.014219ns
|
||||||
|
CHARACTERIZATION_MODE accurate
|
||||||
|
}
|
||||||
@@ -0,0 +1,342 @@
|
|||||||
|
#
|
||||||
|
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||||
|
#
|
||||||
|
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||||
|
#
|
||||||
|
# Use of this Software is subject to the terms and conditions of the
|
||||||
|
# applicable license agreement with ARM Physical IP, Inc.
|
||||||
|
# In addition, this Software is protected by patents, copyright law
|
||||||
|
# and international treaties.
|
||||||
|
#
|
||||||
|
# The copyright notice(s) in this Software does not indicate actual or
|
||||||
|
# intended publication of this Software.
|
||||||
|
#
|
||||||
|
# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
|
||||||
|
#
|
||||||
|
# Creation Date: Sun Oct 13 11:08:28 2019
|
||||||
|
#
|
||||||
|
# Instance Options:
|
||||||
|
# Instance Name: rf2_32x128_wm1
|
||||||
|
# Number of Words: 32
|
||||||
|
# Number of Bits: 128
|
||||||
|
# Multiplexer Width: 2
|
||||||
|
# Multi-Vt selection: LL
|
||||||
|
# Frequency <MHz>: 1
|
||||||
|
# Activity Factor <%>: 50
|
||||||
|
# Pipeline: off
|
||||||
|
# Word-Write Mask: on
|
||||||
|
# Word Partition Size: 1
|
||||||
|
# Write through: off
|
||||||
|
# Top Metal Layer: m5-m10
|
||||||
|
# Power Type: otc
|
||||||
|
# Redundancy: off
|
||||||
|
# Redundant Columns: 2
|
||||||
|
# Redundant Rows: 0
|
||||||
|
# BIST MUXes: on
|
||||||
|
# Soft Error Repair (SER): none
|
||||||
|
# Power Gating: off
|
||||||
|
# Back Biasing: off
|
||||||
|
# Retention: on
|
||||||
|
# Extra Margin Adjustment: on
|
||||||
|
# Advanced Test Features: off
|
||||||
|
# Customer Comment: This is a memory instance
|
||||||
|
# Bus-notation: on
|
||||||
|
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||||
|
# Name Case: upper
|
||||||
|
# Check Instance Name: on
|
||||||
|
# Diodes: on
|
||||||
|
# Drive Strength: 6
|
||||||
|
# Site Definitions: off
|
||||||
|
# Library Name: USERLIB
|
||||||
|
# Liberty setting: nldm
|
||||||
|
#
|
||||||
|
# Compiler Versions:
|
||||||
|
# Memory Version: r0p0
|
||||||
|
# Lang compiler Version: 4.5.1-EAC
|
||||||
|
# View Name: datatable
|
||||||
|
# AMCI Version: 2.0.4-EAC
|
||||||
|
# datatable_memcomp Version: 2.3.2-EAC
|
||||||
|
#
|
||||||
|
# Modeling Assumptions: N/A
|
||||||
|
#
|
||||||
|
# Modeling Limitations: N/A
|
||||||
|
#
|
||||||
|
# Known Bugs: N/A
|
||||||
|
#
|
||||||
|
# Known Work Arounds: N/A
|
||||||
|
#
|
||||||
|
# Units used in Datatable :
|
||||||
|
# geomx: micron
|
||||||
|
# geomy: micron
|
||||||
|
# Voltage: volts
|
||||||
|
# Temprature: Degree Celsius
|
||||||
|
# Current: mA
|
||||||
|
# Time: ns
|
||||||
|
#
|
||||||
|
name ff_0p99v_0p99v_m40c
|
||||||
|
S N
|
||||||
|
geomx 21.9750
|
||||||
|
geomy 414.8600
|
||||||
|
volt 0.9900
|
||||||
|
temp -40.0000
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
|
||||||
|
tcenacenya 0.0756
|
||||||
|
ttcenacenya 0.0754
|
||||||
|
ttenacenyapu 0.1068
|
||||||
|
ttenacenyanu 0.1229
|
||||||
|
tdftrambypcenya 0.1215
|
||||||
|
taaaya 0.0649
|
||||||
|
ttaaaya 0.0657
|
||||||
|
ttenaayapu 0.1204
|
||||||
|
ttenaayanu 0.1113
|
||||||
|
tdftrambypaya 0.1102
|
||||||
|
tcenbcenyb 0.0776
|
||||||
|
ttcenbcenyb 0.0789
|
||||||
|
ttenbcenybpu 0.1132
|
||||||
|
ttenbcenybnu 0.1593
|
||||||
|
tdftrambypcenyb 0.1160
|
||||||
|
twenbwenyb 0.0831
|
||||||
|
ttwenbwenyb 0.0825
|
||||||
|
ttenbwenybpu 0.2299
|
||||||
|
ttenbwenybnu 0.2434
|
||||||
|
tdftrambypwenyb 0.1505
|
||||||
|
tabayb 0.0648
|
||||||
|
ttabayb 0.0652
|
||||||
|
ttenbaybpu 0.1534
|
||||||
|
ttenbaybnu 0.1525
|
||||||
|
tdftrambypayb 0.1080
|
||||||
|
taccqa_rd0 0.3873
|
||||||
|
taccqa_rd1 0.3869
|
||||||
|
taccqa_rd2 0.3863
|
||||||
|
taccqa_rd3 0.3862
|
||||||
|
taccqa_rd4 0.4256
|
||||||
|
taccqa_rd5 0.4537
|
||||||
|
taccqa_rd6 0.4889
|
||||||
|
taccqa_rd7 0.5169
|
||||||
|
taccqa_scan0 0.3873
|
||||||
|
taccqa_scan1 0.3869
|
||||||
|
taccqa_scan2 0.3863
|
||||||
|
taccqa_scan3 0.3862
|
||||||
|
taccqa_scan4 0.4256
|
||||||
|
taccqa_scan5 0.4537
|
||||||
|
taccqa_scan6 0.4889
|
||||||
|
taccqa_scan7 0.5169
|
||||||
|
tclkasoa_rd0 0.4029
|
||||||
|
tclkasoa_rd1 0.4026
|
||||||
|
tclkasoa_rd2 0.4019
|
||||||
|
tclkasoa_rd3 0.4018
|
||||||
|
tclkasoa_rd4 0.4412
|
||||||
|
tclkasoa_rd5 0.4693
|
||||||
|
tclkasoa_rd6 0.5045
|
||||||
|
tclkasoa_rd7 0.5325
|
||||||
|
tclkasoa_scan0 0.4029
|
||||||
|
tclkasoa_scan1 0.4026
|
||||||
|
tclkasoa_scan2 0.4019
|
||||||
|
tclkasoa_scan3 0.4018
|
||||||
|
tclkasoa_scan4 0.4412
|
||||||
|
tclkasoa_scan5 0.4693
|
||||||
|
tclkasoa_scan6 0.5045
|
||||||
|
tclkasoa_scan7 0.5325
|
||||||
|
tclkbsob 0.2114
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Kload specific information.
|
||||||
|
kload_cenya 1.5204
|
||||||
|
kload_aya 1.2343
|
||||||
|
kload_cenyb 1.4733
|
||||||
|
kload_wenyb 1.2670
|
||||||
|
kload_ayb 1.2581
|
||||||
|
kload_qa 0.4461
|
||||||
|
kload_soa 1.2646
|
||||||
|
kload_sob 1.3026
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Cycle time specific information.
|
||||||
|
tcyca_ema0 0.5528
|
||||||
|
tcyca_ema1 0.5525
|
||||||
|
tcyca_ema2 0.5518
|
||||||
|
tcyca_ema3 0.5517
|
||||||
|
tcyca_ema4 0.5912
|
||||||
|
tcyca_ema5 0.6193
|
||||||
|
tcyca_ema6 0.6546
|
||||||
|
tcyca_ema7 0.6826
|
||||||
|
tcycb_ema0 0.5623
|
||||||
|
tcycb_ema1 0.5654
|
||||||
|
tcycb_ema2 0.5675
|
||||||
|
tcycb_ema3 0.5718
|
||||||
|
tcycb_ema4 0.6191
|
||||||
|
tcycb_ema5 0.6469
|
||||||
|
tcycb_ema6 0.6893
|
||||||
|
tcycb_ema7 0.7174
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Clock collision specific information.
|
||||||
|
tcracwb_rd0 0.3927
|
||||||
|
tcracwb_rd1 0.3924
|
||||||
|
tcracwb_rd2 0.3917
|
||||||
|
tcracwb_rd3 0.3916
|
||||||
|
tcracwb_rd4 0.4311
|
||||||
|
tcracwb_rd5 0.4592
|
||||||
|
tcracwb_rd6 0.4944
|
||||||
|
tcracwb_rd7 0.5224
|
||||||
|
tcwbcra_wr0 0.4695
|
||||||
|
tcwbcra_wr1 0.4726
|
||||||
|
tcwbcra_wr2 0.4747
|
||||||
|
tcwbcra_wr3 0.4790
|
||||||
|
tcwbcra_wr4 0.5262
|
||||||
|
tcwbcra_wr5 0.5540
|
||||||
|
tcwbcra_wr6 0.5964
|
||||||
|
tcwbcra_wr7 0.6244
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Pulse width specific information.
|
||||||
|
tckah 0.0899
|
||||||
|
tckal 0.0871
|
||||||
|
tckbh 0.0886
|
||||||
|
tckbl 0.0843
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Setup time specific information.
|
||||||
|
tcenas 0.0849
|
||||||
|
taas 0.0866
|
||||||
|
taas_colldisn0 0.0866
|
||||||
|
tcenbs 0.0917
|
||||||
|
twenbs 0.0082
|
||||||
|
tabs 0.0910
|
||||||
|
tabs_colldisn0 0.0910
|
||||||
|
tdbs 0.0283
|
||||||
|
temaas 0.5758
|
||||||
|
temasas 0.5758
|
||||||
|
temabs 0.5958
|
||||||
|
ttenas 0.1554
|
||||||
|
ttcenas 0.0849
|
||||||
|
ttaas 0.0880
|
||||||
|
ttaas_colldisn0 0.0880
|
||||||
|
ttenbs 0.3531
|
||||||
|
ttcenbs 0.0930
|
||||||
|
ttwenbs 0.0084
|
||||||
|
ttabs 0.0924
|
||||||
|
ttabs_colldisn0 0.0924
|
||||||
|
ttdbs 0.0283
|
||||||
|
tsias 0.1710
|
||||||
|
tseas 0.1710
|
||||||
|
tdftrambypas 0.2057
|
||||||
|
tdftrambypbs 0.2057
|
||||||
|
tsibs 0.0283
|
||||||
|
tsebs 0.3531
|
||||||
|
tcolldisnas 0.5758
|
||||||
|
tcolldisnbs 0.5958
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Hold time specific information.
|
||||||
|
tcenah 0.0376
|
||||||
|
tcenaf_ret1nfh 0.5948
|
||||||
|
tcenaf_ret1nrh 0.2791
|
||||||
|
taah 0.0643
|
||||||
|
taah_colldisn0 0.0643
|
||||||
|
tcenbh 0.0340
|
||||||
|
tcenbf_ret1nfh 0.5948
|
||||||
|
tcenbf_ret1nrh 0.2791
|
||||||
|
twenbh 0.1564
|
||||||
|
tabh 0.0531
|
||||||
|
tabh_colldisn0 0.0531
|
||||||
|
tdbh 0.1602
|
||||||
|
temaah 0.7560
|
||||||
|
temasah 0.7560
|
||||||
|
temabh 0.7403
|
||||||
|
ttenah 0.0707
|
||||||
|
ttcenah 0.0378
|
||||||
|
ttcenaf_ret1nfh 0.5948
|
||||||
|
ttcenaf_ret1nrh 0.2791
|
||||||
|
ttaah 0.0643
|
||||||
|
ttaah_colldisn0 0.0643
|
||||||
|
ttenbh 0.1766
|
||||||
|
ttcenbh 0.0340
|
||||||
|
ttcenbf_ret1nfh 0.5948
|
||||||
|
ttcenbf_ret1nrh 0.2791
|
||||||
|
ttwenbh 0.1569
|
||||||
|
ttabh 0.0531
|
||||||
|
ttabh_colldisn0 0.0531
|
||||||
|
ttdbh 0.1605
|
||||||
|
tret1nf_dftrambypfh 0.0232
|
||||||
|
tret1nr_dftrambypfh 0.5948
|
||||||
|
tret1nf_cenbrh 0.0232
|
||||||
|
tret1nf_cenarh 0.0212
|
||||||
|
tret1nf_tcenarh 0.0212
|
||||||
|
tret1nf_tcenbrh 0.0232
|
||||||
|
tret1nr_tcenbrh 0.5948
|
||||||
|
tret1nr_tcenarh 0.5747
|
||||||
|
tret1nr_cenbrh 0.5948
|
||||||
|
tret1nr_cenarh 0.5747
|
||||||
|
tsiah 0.0543
|
||||||
|
tseah 0.7560
|
||||||
|
tdftrambypah 0.7560
|
||||||
|
tdftrambypbh 0.5948
|
||||||
|
tdftrambypr_ret1nfh 0.5948
|
||||||
|
tdftrambypr_ret1nrh 0.2791
|
||||||
|
tsibh 0.1602
|
||||||
|
tsebh 0.1766
|
||||||
|
tcolldisnah 0.7560
|
||||||
|
tcolldisnbh 0.7403
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
|
||||||
|
icap_clka 0.0076
|
||||||
|
icap_cena 0.0012
|
||||||
|
icap_aa 0.0012
|
||||||
|
icap_clkb 0.0076
|
||||||
|
icap_cenb 0.0013
|
||||||
|
icap_wenb 0.0014
|
||||||
|
icap_ab 0.0012
|
||||||
|
icap_db 0.0015
|
||||||
|
icap_emaa 0.0044
|
||||||
|
icap_emasa 0.0018
|
||||||
|
icap_emab 0.0043
|
||||||
|
icap_tena 0.0009
|
||||||
|
icap_tcena 0.0012
|
||||||
|
icap_taa 0.0012
|
||||||
|
icap_tenb 0.0009
|
||||||
|
icap_tcenb 0.0014
|
||||||
|
icap_twenb 0.0012
|
||||||
|
icap_tab 0.0012
|
||||||
|
icap_tdb 0.0013
|
||||||
|
icap_sia 0.0011
|
||||||
|
icap_sea 0.0015
|
||||||
|
icap_dftrambyp 0.0017
|
||||||
|
icap_sib 0.0041
|
||||||
|
icap_seb 0.0015
|
||||||
|
icap_colldisn 0.0018
|
||||||
|
icap_ret1n 0.0028
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : current specific information.
|
||||||
|
icc_standby_c_chipdisable 2.292e-03
|
||||||
|
icc_standby_p_chipdisable 9.632e-03
|
||||||
|
icc_standby_c_selective_precharge 2.277e-03
|
||||||
|
icc_standby_p_selective_precharge 8.341e-03
|
||||||
|
icc_standby_c_ret1 2.260e-03
|
||||||
|
icc_standby_p_ret1 8.341e-04
|
||||||
|
icc_c_rd0_a 9.165e-05
|
||||||
|
icc_c_rd1_a 9.165e-05
|
||||||
|
icc_c_rd2_a 9.165e-05
|
||||||
|
icc_c_rd3_a 9.165e-05
|
||||||
|
icc_c_rd4_a 9.432e-05
|
||||||
|
icc_c_rd5_a 9.585e-05
|
||||||
|
icc_c_rd6_a 9.741e-05
|
||||||
|
icc_c_rd7_a 9.814e-05
|
||||||
|
icc_p_rd0_a 3.597e-03
|
||||||
|
icc_p_rd1_a 3.597e-03
|
||||||
|
icc_p_rd2_a 3.597e-03
|
||||||
|
icc_p_rd3_a 3.597e-03
|
||||||
|
icc_p_rd4_a 3.605e-03
|
||||||
|
icc_p_rd5_a 3.609e-03
|
||||||
|
icc_p_rd6_a 3.613e-03
|
||||||
|
icc_p_rd7_a 3.616e-03
|
||||||
|
icc_c_wr0_b 2.175e-04
|
||||||
|
icc_c_wr1_b 2.175e-04
|
||||||
|
icc_c_wr2_b 2.175e-04
|
||||||
|
icc_c_wr3_b 2.175e-04
|
||||||
|
icc_c_wr4_b 2.202e-04
|
||||||
|
icc_c_wr5_b 2.218e-04
|
||||||
|
icc_c_wr6_b 2.233e-04
|
||||||
|
icc_c_wr7_b 2.241e-04
|
||||||
|
icc_p_wr0_b 4.929e-03
|
||||||
|
icc_p_wr1_b 4.929e-03
|
||||||
|
icc_p_wr2_b 4.929e-03
|
||||||
|
icc_p_wr3_b 4.929e-03
|
||||||
|
icc_p_wr4_b 4.933e-03
|
||||||
|
icc_p_wr5_b 4.938e-03
|
||||||
|
icc_p_wr6_b 4.941e-03
|
||||||
|
icc_p_wr7_b 4.944e-03
|
||||||
|
icc_c_desela 0.000e+00
|
||||||
|
icc_p_desela 6.445e-05
|
||||||
|
icc_c_deselb 0.000e+00
|
||||||
|
icc_p_deselb 1.157e-03
|
||||||
|
icc_c_peak 5.755785
|
||||||
|
icc_p_peak 75.373305
|
||||||
|
icc_c_inrush 2.053631
|
||||||
|
icc_p_inrush 40.179487
|
||||||
File diff suppressed because it is too large
Load Diff
275
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_rtl.v
Normal file
275
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_rtl.v
Normal file
@@ -0,0 +1,275 @@
|
|||||||
|
/* verilog_rtl_memcomp Version: c0.1.0-EAC */
|
||||||
|
/* common_memcomp Version: c0.1.2-EAC */
|
||||||
|
/* lang compiler Version: 4.5.1-EAC Nov 6 2014 16:10:45 */
|
||||||
|
//
|
||||||
|
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||||
|
//
|
||||||
|
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||||
|
//
|
||||||
|
// Use of this Software is subject to the terms and conditions of the
|
||||||
|
// applicable license agreement with ARM Physical IP, Inc.
|
||||||
|
// In addition, this Software is protected by patents, copyright law
|
||||||
|
// and international treaties.
|
||||||
|
//
|
||||||
|
// The copyright notice(s) in this Software does not indicate actual or
|
||||||
|
// intended publication of this Software.
|
||||||
|
//
|
||||||
|
// Repair Verilog RTL for High Capacity Two Port Register File SVT MVT Compiler
|
||||||
|
//
|
||||||
|
// Instance Name: rf2_32x128_wm1_rtl_top
|
||||||
|
// Words: 32
|
||||||
|
// User Bits: 128
|
||||||
|
// Mux: 2
|
||||||
|
// Drive: 6
|
||||||
|
// Write Mask: On
|
||||||
|
// Extra Margin Adjustment: On
|
||||||
|
// Redundancy: off
|
||||||
|
// Redundant Rows: 0
|
||||||
|
// Redundant Columns: 2
|
||||||
|
// Test Muxes On
|
||||||
|
// Ser: none
|
||||||
|
// Retention: on
|
||||||
|
// Power Gating: off
|
||||||
|
//
|
||||||
|
// Creation Date: Sun Oct 13 11:09:26 2019
|
||||||
|
// Version: r0p0
|
||||||
|
//
|
||||||
|
// Verified
|
||||||
|
//
|
||||||
|
// Known Bugs: None.
|
||||||
|
//
|
||||||
|
// Known Work Arounds: N/A
|
||||||
|
//
|
||||||
|
`timescale 1ns/1ps
|
||||||
|
|
||||||
|
module rf2_32x128_wm1_rtl_top (
|
||||||
|
CENYA,
|
||||||
|
AYA,
|
||||||
|
CENYB,
|
||||||
|
WENYB,
|
||||||
|
AYB,
|
||||||
|
QA,
|
||||||
|
SOA,
|
||||||
|
SOB,
|
||||||
|
CLKA,
|
||||||
|
CENA,
|
||||||
|
AA,
|
||||||
|
CLKB,
|
||||||
|
CENB,
|
||||||
|
WENB,
|
||||||
|
AB,
|
||||||
|
DB,
|
||||||
|
EMAA,
|
||||||
|
EMASA,
|
||||||
|
EMAB,
|
||||||
|
TENA,
|
||||||
|
TCENA,
|
||||||
|
TAA,
|
||||||
|
TENB,
|
||||||
|
TCENB,
|
||||||
|
TWENB,
|
||||||
|
TAB,
|
||||||
|
TDB,
|
||||||
|
RET1N,
|
||||||
|
SIA,
|
||||||
|
SEA,
|
||||||
|
DFTRAMBYP,
|
||||||
|
SIB,
|
||||||
|
SEB,
|
||||||
|
COLLDISN
|
||||||
|
);
|
||||||
|
|
||||||
|
output CENYA;
|
||||||
|
output [4:0] AYA;
|
||||||
|
output CENYB;
|
||||||
|
output [127:0] WENYB;
|
||||||
|
output [4:0] AYB;
|
||||||
|
output [127:0] QA;
|
||||||
|
output [1:0] SOA;
|
||||||
|
output [1:0] SOB;
|
||||||
|
input CLKA;
|
||||||
|
input CENA;
|
||||||
|
input [4:0] AA;
|
||||||
|
input CLKB;
|
||||||
|
input CENB;
|
||||||
|
input [127:0] WENB;
|
||||||
|
input [4:0] AB;
|
||||||
|
input [127:0] DB;
|
||||||
|
input [2:0] EMAA;
|
||||||
|
input EMASA;
|
||||||
|
input [2:0] EMAB;
|
||||||
|
input TENA;
|
||||||
|
input TCENA;
|
||||||
|
input [4:0] TAA;
|
||||||
|
input TENB;
|
||||||
|
input TCENB;
|
||||||
|
input [127:0] TWENB;
|
||||||
|
input [4:0] TAB;
|
||||||
|
input [127:0] TDB;
|
||||||
|
input RET1N;
|
||||||
|
input [1:0] SIA;
|
||||||
|
input SEA;
|
||||||
|
input DFTRAMBYP;
|
||||||
|
input [1:0] SIB;
|
||||||
|
input SEB;
|
||||||
|
input COLLDISN;
|
||||||
|
wire [127:0] QOA;
|
||||||
|
wire [127:0] DIB;
|
||||||
|
|
||||||
|
assign QA = QOA;
|
||||||
|
assign DIB = DB;
|
||||||
|
rf2_32x128_wm1_fr_top u0 (
|
||||||
|
.CENYA(CENYA),
|
||||||
|
.AYA(AYA),
|
||||||
|
.CENYB(CENYB),
|
||||||
|
.WENYB(WENYB),
|
||||||
|
.AYB(AYB),
|
||||||
|
.QOA(QOA),
|
||||||
|
.SOA(SOA),
|
||||||
|
.SOB(SOB),
|
||||||
|
.CLKA(CLKA),
|
||||||
|
.CENA(CENA),
|
||||||
|
.AA(AA),
|
||||||
|
.CLKB(CLKB),
|
||||||
|
.CENB(CENB),
|
||||||
|
.WENB(WENB),
|
||||||
|
.AB(AB),
|
||||||
|
.DIB(DIB),
|
||||||
|
.EMAA(EMAA),
|
||||||
|
.EMASA(EMASA),
|
||||||
|
.EMAB(EMAB),
|
||||||
|
.TENA(TENA),
|
||||||
|
.TCENA(TCENA),
|
||||||
|
.TAA(TAA),
|
||||||
|
.TENB(TENB),
|
||||||
|
.TCENB(TCENB),
|
||||||
|
.TWENB(TWENB),
|
||||||
|
.TAB(TAB),
|
||||||
|
.TDB(TDB),
|
||||||
|
.RET1N(RET1N),
|
||||||
|
.SIA(SIA),
|
||||||
|
.SEA(SEA),
|
||||||
|
.DFTRAMBYP(DFTRAMBYP),
|
||||||
|
.SIB(SIB),
|
||||||
|
.SEB(SEB),
|
||||||
|
.COLLDISN(COLLDISN)
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
module rf2_32x128_wm1_fr_top (
|
||||||
|
CENYA,
|
||||||
|
AYA,
|
||||||
|
CENYB,
|
||||||
|
WENYB,
|
||||||
|
AYB,
|
||||||
|
QOA,
|
||||||
|
SOA,
|
||||||
|
SOB,
|
||||||
|
CLKA,
|
||||||
|
CENA,
|
||||||
|
AA,
|
||||||
|
CLKB,
|
||||||
|
CENB,
|
||||||
|
WENB,
|
||||||
|
AB,
|
||||||
|
DIB,
|
||||||
|
EMAA,
|
||||||
|
EMASA,
|
||||||
|
EMAB,
|
||||||
|
TENA,
|
||||||
|
TCENA,
|
||||||
|
TAA,
|
||||||
|
TENB,
|
||||||
|
TCENB,
|
||||||
|
TWENB,
|
||||||
|
TAB,
|
||||||
|
TDB,
|
||||||
|
RET1N,
|
||||||
|
SIA,
|
||||||
|
SEA,
|
||||||
|
DFTRAMBYP,
|
||||||
|
SIB,
|
||||||
|
SEB,
|
||||||
|
COLLDISN
|
||||||
|
);
|
||||||
|
|
||||||
|
output CENYA;
|
||||||
|
output [4:0] AYA;
|
||||||
|
output CENYB;
|
||||||
|
output [127:0] WENYB;
|
||||||
|
output [4:0] AYB;
|
||||||
|
output [127:0] QOA;
|
||||||
|
output [1:0] SOA;
|
||||||
|
output [1:0] SOB;
|
||||||
|
input CLKA;
|
||||||
|
input CENA;
|
||||||
|
input [4:0] AA;
|
||||||
|
input CLKB;
|
||||||
|
input CENB;
|
||||||
|
input [127:0] WENB;
|
||||||
|
input [4:0] AB;
|
||||||
|
input [127:0] DIB;
|
||||||
|
input [2:0] EMAA;
|
||||||
|
input EMASA;
|
||||||
|
input [2:0] EMAB;
|
||||||
|
input TENA;
|
||||||
|
input TCENA;
|
||||||
|
input [4:0] TAA;
|
||||||
|
input TENB;
|
||||||
|
input TCENB;
|
||||||
|
input [127:0] TWENB;
|
||||||
|
input [4:0] TAB;
|
||||||
|
input [127:0] TDB;
|
||||||
|
input RET1N;
|
||||||
|
input [1:0] SIA;
|
||||||
|
input SEA;
|
||||||
|
input DFTRAMBYP;
|
||||||
|
input [1:0] SIB;
|
||||||
|
input SEB;
|
||||||
|
input COLLDISN;
|
||||||
|
|
||||||
|
wire [127:0] DB;
|
||||||
|
wire [127:0] QA;
|
||||||
|
|
||||||
|
assign DB=DIB;
|
||||||
|
assign QOA=QA;
|
||||||
|
rf2_32x128_wm1 u0 (
|
||||||
|
.CENYA(CENYA),
|
||||||
|
.AYA(AYA),
|
||||||
|
.CENYB(CENYB),
|
||||||
|
.WENYB(WENYB),
|
||||||
|
.AYB(AYB),
|
||||||
|
.QA(QA),
|
||||||
|
.SOA(SOA),
|
||||||
|
.SOB(SOB),
|
||||||
|
.CLKA(CLKA),
|
||||||
|
.CENA(CENA),
|
||||||
|
.AA(AA),
|
||||||
|
.CLKB(CLKB),
|
||||||
|
.CENB(CENB),
|
||||||
|
.WENB(WENB),
|
||||||
|
.AB(AB),
|
||||||
|
.DB(DB),
|
||||||
|
.EMAA(EMAA),
|
||||||
|
.EMASA(EMASA),
|
||||||
|
.EMAB(EMAB),
|
||||||
|
.TENA(TENA),
|
||||||
|
.TCENA(TCENA),
|
||||||
|
.TAA(TAA),
|
||||||
|
.TENB(TENB),
|
||||||
|
.TCENB(TCENB),
|
||||||
|
.TWENB(TWENB),
|
||||||
|
.TAB(TAB),
|
||||||
|
.TDB(TDB),
|
||||||
|
.RET1N(RET1N),
|
||||||
|
.SIA(SIA),
|
||||||
|
.SEA(SEA),
|
||||||
|
.DFTRAMBYP(DFTRAMBYP),
|
||||||
|
.SIB(SIB),
|
||||||
|
.SEB(SEB),
|
||||||
|
.COLLDISN(COLLDISN)
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule // rf2_32x128_wm1_fr_top
|
||||||
|
|
||||||
@@ -0,0 +1,162 @@
|
|||||||
|
#
|
||||||
|
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||||
|
#
|
||||||
|
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||||
|
#
|
||||||
|
# Use of this Software is subject to the terms and conditions of the
|
||||||
|
# applicable license agreement with ARM Physical IP, Inc.
|
||||||
|
# In addition, this Software is protected by patents, copyright law
|
||||||
|
# and international treaties.
|
||||||
|
#
|
||||||
|
# The copyright notice(s) in this Software does not indicate actual or
|
||||||
|
# intended publication of this Software.
|
||||||
|
#
|
||||||
|
# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
|
||||||
|
#
|
||||||
|
# Creation Date: Sun Oct 13 11:08:07 2019
|
||||||
|
#
|
||||||
|
# Instance Options:
|
||||||
|
# Instance Name: rf2_32x128_wm1
|
||||||
|
# Number of Words: 32
|
||||||
|
# Number of Bits: 128
|
||||||
|
# Multiplexer Width: 2
|
||||||
|
# Multi-Vt selection: LL
|
||||||
|
# Frequency <MHz>: 1
|
||||||
|
# Activity Factor <%>: 50
|
||||||
|
# Pipeline: off
|
||||||
|
# Word-Write Mask: on
|
||||||
|
# Word Partition Size: 1
|
||||||
|
# Write through: off
|
||||||
|
# Top Metal Layer: m5-m10
|
||||||
|
# Power Type: otc
|
||||||
|
# Redundancy: off
|
||||||
|
# Redundant Columns: 2
|
||||||
|
# Redundant Rows: 0
|
||||||
|
# BIST MUXes: on
|
||||||
|
# Soft Error Repair (SER): none
|
||||||
|
# Power Gating: off
|
||||||
|
# Back Biasing: off
|
||||||
|
# Retention: on
|
||||||
|
# Extra Margin Adjustment: on
|
||||||
|
# Advanced Test Features: off
|
||||||
|
# Customer Comment: This is a memory instance
|
||||||
|
# Bus-notation: on
|
||||||
|
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||||
|
# Name Case: upper
|
||||||
|
# Check Instance Name: on
|
||||||
|
# Diodes: on
|
||||||
|
# Drive Strength: 6
|
||||||
|
# Site Definitions: off
|
||||||
|
# Library Name: USERLIB
|
||||||
|
# Liberty setting: nldm
|
||||||
|
#
|
||||||
|
# Compiler Versions:
|
||||||
|
# Memory Version: r0p0
|
||||||
|
# Lang compiler Version: 4.5.1-EAC
|
||||||
|
# View Name: avm
|
||||||
|
# AMCI Version: 2.0.4-EAC
|
||||||
|
# avm_memcomp Version: 2.3.7-EAC
|
||||||
|
#
|
||||||
|
# Modeling Assumptions: N/A
|
||||||
|
#
|
||||||
|
# Modeling Limitations: N/A
|
||||||
|
#
|
||||||
|
# Known Bugs: N/A
|
||||||
|
#
|
||||||
|
# Known Work Arounds: N/A
|
||||||
|
#
|
||||||
|
rf2_32x128_wm1 {
|
||||||
|
MEMORY_TYPE RegFile
|
||||||
|
EQUIV_GATE_COUNT 4506
|
||||||
|
VDD_PIN VDDCE VDDPE
|
||||||
|
GND_PIN VSSE
|
||||||
|
#This file is for PROCESS SS, CORNER SS_0P81V_0P81V_125C
|
||||||
|
#However, RedHawk needs the process to be specified as 'PROCESS XX'
|
||||||
|
PROCESS XX
|
||||||
|
Cload 3.5e-05nF
|
||||||
|
VDD 0.81 0.81
|
||||||
|
|
||||||
|
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
|
||||||
|
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
|
||||||
|
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||||
|
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
|
||||||
|
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||||
|
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
|
||||||
|
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
|
||||||
|
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
|
||||||
|
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
|
||||||
|
|
||||||
|
Cpd avm_into_lowpwr {
|
||||||
|
VDDCE VSSE 5.71087e-05nF
|
||||||
|
VDDPE VSSE 6.28090e-04nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_into_lowpwr {
|
||||||
|
VDDCE VSSE 0.85138mA
|
||||||
|
VDDPE VSSE 3.68611mA
|
||||||
|
}
|
||||||
|
Cpd avm_outof_lowpwr {
|
||||||
|
VDDCE VSSE 6.28195e-05nF
|
||||||
|
VDDPE VSSE 5.76153e-03nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_outof_lowpwr {
|
||||||
|
VDDCE VSSE 0.93652mA
|
||||||
|
VDDPE VSSE 23.15579mA
|
||||||
|
}
|
||||||
|
Cpd avm_read_write {
|
||||||
|
VDDCE VSSE 2.89952e-04nF
|
||||||
|
VDDPE VSSE 8.92025e-03nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_read_write {
|
||||||
|
VDDCE VSSE 2.22663mA
|
||||||
|
VDDPE VSSE 24.23907mA
|
||||||
|
}
|
||||||
|
Cpd avm_read_desel {
|
||||||
|
VDDCE VSSE 1.06570e-04nF
|
||||||
|
VDDPE VSSE 3.74491e-03nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_read_desel {
|
||||||
|
VDDCE VSSE 1.06930mA
|
||||||
|
VDDPE VSSE 12.67500mA
|
||||||
|
}
|
||||||
|
Cpd avm_desel_write {
|
||||||
|
VDDCE VSSE 1.83382e-04nF
|
||||||
|
VDDPE VSSE 5.17534e-03nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_desel_write {
|
||||||
|
VDDCE VSSE 1.19590mA
|
||||||
|
VDDPE VSSE 16.68900mA
|
||||||
|
}
|
||||||
|
Cpd avm_scan_capture {
|
||||||
|
VDDCE VSSE 9.83176e-06nF
|
||||||
|
VDDPE VSSE 1.13987e-02nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_scan_capture {
|
||||||
|
VDDCE VSSE 0.19692mA
|
||||||
|
VDDPE VSSE 16.41292mA
|
||||||
|
}
|
||||||
|
Cpd avm_scan_shift {
|
||||||
|
VDDCE VSSE 9.83176e-06nF
|
||||||
|
VDDPE VSSE 1.13987e-02nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_scan_shift {
|
||||||
|
VDDCE VSSE 0.19692mA
|
||||||
|
VDDPE VSSE 16.41292mA
|
||||||
|
}
|
||||||
|
Cpd standby_trig {
|
||||||
|
VDDCE VSSE 0.00000e+00nF
|
||||||
|
VDDPE VSSE 2.47655e-06nF
|
||||||
|
}
|
||||||
|
Cpd standby_ntrig {
|
||||||
|
VDDCE VSSE 0.00000e+00nF
|
||||||
|
VDDPE VSSE 2.25737e-05nF
|
||||||
|
}
|
||||||
|
LEAKAGE_I {
|
||||||
|
VDDCE VSSE 1.39840e-02mA
|
||||||
|
VDDPE VSSE 0.11891mA
|
||||||
|
}
|
||||||
|
tsu 0.184945ns
|
||||||
|
ck2q_delay 0.724564ns
|
||||||
|
tr_q 0.036986ns
|
||||||
|
tf_q 0.041705ns
|
||||||
|
CHARACTERIZATION_MODE accurate
|
||||||
|
}
|
||||||
@@ -0,0 +1,342 @@
|
|||||||
|
#
|
||||||
|
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||||
|
#
|
||||||
|
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||||
|
#
|
||||||
|
# Use of this Software is subject to the terms and conditions of the
|
||||||
|
# applicable license agreement with ARM Physical IP, Inc.
|
||||||
|
# In addition, this Software is protected by patents, copyright law
|
||||||
|
# and international treaties.
|
||||||
|
#
|
||||||
|
# The copyright notice(s) in this Software does not indicate actual or
|
||||||
|
# intended publication of this Software.
|
||||||
|
#
|
||||||
|
# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
|
||||||
|
#
|
||||||
|
# Creation Date: Sun Oct 13 11:08:34 2019
|
||||||
|
#
|
||||||
|
# Instance Options:
|
||||||
|
# Instance Name: rf2_32x128_wm1
|
||||||
|
# Number of Words: 32
|
||||||
|
# Number of Bits: 128
|
||||||
|
# Multiplexer Width: 2
|
||||||
|
# Multi-Vt selection: LL
|
||||||
|
# Frequency <MHz>: 1
|
||||||
|
# Activity Factor <%>: 50
|
||||||
|
# Pipeline: off
|
||||||
|
# Word-Write Mask: on
|
||||||
|
# Word Partition Size: 1
|
||||||
|
# Write through: off
|
||||||
|
# Top Metal Layer: m5-m10
|
||||||
|
# Power Type: otc
|
||||||
|
# Redundancy: off
|
||||||
|
# Redundant Columns: 2
|
||||||
|
# Redundant Rows: 0
|
||||||
|
# BIST MUXes: on
|
||||||
|
# Soft Error Repair (SER): none
|
||||||
|
# Power Gating: off
|
||||||
|
# Back Biasing: off
|
||||||
|
# Retention: on
|
||||||
|
# Extra Margin Adjustment: on
|
||||||
|
# Advanced Test Features: off
|
||||||
|
# Customer Comment: This is a memory instance
|
||||||
|
# Bus-notation: on
|
||||||
|
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||||
|
# Name Case: upper
|
||||||
|
# Check Instance Name: on
|
||||||
|
# Diodes: on
|
||||||
|
# Drive Strength: 6
|
||||||
|
# Site Definitions: off
|
||||||
|
# Library Name: USERLIB
|
||||||
|
# Liberty setting: nldm
|
||||||
|
#
|
||||||
|
# Compiler Versions:
|
||||||
|
# Memory Version: r0p0
|
||||||
|
# Lang compiler Version: 4.5.1-EAC
|
||||||
|
# View Name: datatable
|
||||||
|
# AMCI Version: 2.0.4-EAC
|
||||||
|
# datatable_memcomp Version: 2.3.2-EAC
|
||||||
|
#
|
||||||
|
# Modeling Assumptions: N/A
|
||||||
|
#
|
||||||
|
# Modeling Limitations: N/A
|
||||||
|
#
|
||||||
|
# Known Bugs: N/A
|
||||||
|
#
|
||||||
|
# Known Work Arounds: N/A
|
||||||
|
#
|
||||||
|
# Units used in Datatable :
|
||||||
|
# geomx: micron
|
||||||
|
# geomy: micron
|
||||||
|
# Voltage: volts
|
||||||
|
# Temprature: Degree Celsius
|
||||||
|
# Current: mA
|
||||||
|
# Time: ns
|
||||||
|
#
|
||||||
|
name ss_0p81v_0p81v_125c
|
||||||
|
S N
|
||||||
|
geomx 21.9750
|
||||||
|
geomy 414.8600
|
||||||
|
volt 0.8100
|
||||||
|
temp 125.0000
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
|
||||||
|
tcenacenya 0.1698
|
||||||
|
ttcenacenya 0.1694
|
||||||
|
ttenacenyapu 0.2569
|
||||||
|
ttenacenyanu 0.3113
|
||||||
|
tdftrambypcenya 0.3774
|
||||||
|
taaaya 0.1761
|
||||||
|
ttaaaya 0.1785
|
||||||
|
ttenaayapu 0.3543
|
||||||
|
ttenaayanu 0.3264
|
||||||
|
tdftrambypaya 0.3634
|
||||||
|
tcenbcenyb 0.1739
|
||||||
|
ttcenbcenyb 0.1753
|
||||||
|
ttenbcenybpu 0.2627
|
||||||
|
ttenbcenybnu 0.4940
|
||||||
|
tdftrambypcenyb 0.3766
|
||||||
|
twenbwenyb 0.2544
|
||||||
|
ttwenbwenyb 0.2549
|
||||||
|
ttenbwenybpu 0.6549
|
||||||
|
ttenbwenybnu 0.6651
|
||||||
|
tdftrambypwenyb 0.3809
|
||||||
|
tabayb 0.1767
|
||||||
|
ttabayb 0.1803
|
||||||
|
ttenbaybpu 0.5579
|
||||||
|
ttenbaybnu 0.5197
|
||||||
|
tdftrambypayb 0.3592
|
||||||
|
taccqa_rd0 0.7072
|
||||||
|
taccqa_rd1 0.7115
|
||||||
|
taccqa_rd2 0.7168
|
||||||
|
taccqa_rd3 0.7246
|
||||||
|
taccqa_rd4 0.8255
|
||||||
|
taccqa_rd5 0.9233
|
||||||
|
taccqa_rd6 1.0320
|
||||||
|
taccqa_rd7 1.1298
|
||||||
|
taccqa_scan0 0.7072
|
||||||
|
taccqa_scan1 0.7115
|
||||||
|
taccqa_scan2 0.7168
|
||||||
|
taccqa_scan3 0.7246
|
||||||
|
taccqa_scan4 0.8255
|
||||||
|
taccqa_scan5 0.9233
|
||||||
|
taccqa_scan6 1.0320
|
||||||
|
taccqa_scan7 1.1298
|
||||||
|
tclkasoa_rd0 0.7968
|
||||||
|
tclkasoa_rd1 0.8011
|
||||||
|
tclkasoa_rd2 0.8064
|
||||||
|
tclkasoa_rd3 0.8142
|
||||||
|
tclkasoa_rd4 0.9152
|
||||||
|
tclkasoa_rd5 1.0130
|
||||||
|
tclkasoa_rd6 1.1217
|
||||||
|
tclkasoa_rd7 1.2196
|
||||||
|
tclkasoa_scan0 0.7968
|
||||||
|
tclkasoa_scan1 0.8011
|
||||||
|
tclkasoa_scan2 0.8064
|
||||||
|
tclkasoa_scan3 0.8142
|
||||||
|
tclkasoa_scan4 0.9152
|
||||||
|
tclkasoa_scan5 1.0130
|
||||||
|
tclkasoa_scan6 1.1217
|
||||||
|
tclkasoa_scan7 1.2196
|
||||||
|
tclkbsob 0.4309
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Kload specific information.
|
||||||
|
kload_cenya 2.9544
|
||||||
|
kload_aya 2.6289
|
||||||
|
kload_cenyb 2.9646
|
||||||
|
kload_wenyb 2.6826
|
||||||
|
kload_ayb 2.6397
|
||||||
|
kload_qa 1.0456
|
||||||
|
kload_soa 2.6921
|
||||||
|
kload_sob 3.0759
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Cycle time specific information.
|
||||||
|
tcyca_ema0 1.1173
|
||||||
|
tcyca_ema1 1.1218
|
||||||
|
tcyca_ema2 1.1273
|
||||||
|
tcyca_ema3 1.1354
|
||||||
|
tcyca_ema4 1.2406
|
||||||
|
tcyca_ema5 1.3425
|
||||||
|
tcyca_ema6 1.4559
|
||||||
|
tcyca_ema7 1.5578
|
||||||
|
tcycb_ema0 1.1869
|
||||||
|
tcycb_ema1 1.1955
|
||||||
|
tcycb_ema2 1.2067
|
||||||
|
tcycb_ema3 1.2169
|
||||||
|
tcycb_ema4 1.3370
|
||||||
|
tcycb_ema5 1.4353
|
||||||
|
tcycb_ema6 1.5677
|
||||||
|
tcycb_ema7 1.6682
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Clock collision specific information.
|
||||||
|
tcracwb_rd0 0.5452
|
||||||
|
tcracwb_rd1 0.5495
|
||||||
|
tcracwb_rd2 0.5548
|
||||||
|
tcracwb_rd3 0.5626
|
||||||
|
tcracwb_rd4 0.6635
|
||||||
|
tcracwb_rd5 0.7613
|
||||||
|
tcracwb_rd6 0.8700
|
||||||
|
tcracwb_rd7 0.9678
|
||||||
|
tcwbcra_wr0 0.8066
|
||||||
|
tcwbcra_wr1 0.8148
|
||||||
|
tcwbcra_wr2 0.8255
|
||||||
|
tcwbcra_wr3 0.8354
|
||||||
|
tcwbcra_wr4 0.9505
|
||||||
|
tcwbcra_wr5 1.0448
|
||||||
|
tcwbcra_wr6 1.1719
|
||||||
|
tcwbcra_wr7 1.2683
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Pulse width specific information.
|
||||||
|
tckah 0.1610
|
||||||
|
tckal 0.1731
|
||||||
|
tckbh 0.1602
|
||||||
|
tckbl 0.1727
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Setup time specific information.
|
||||||
|
tcenas 0.1727
|
||||||
|
taas 0.2271
|
||||||
|
taas_colldisn0 0.2271
|
||||||
|
tcenbs 0.1749
|
||||||
|
twenbs 0.0805
|
||||||
|
tabs 0.2247
|
||||||
|
tabs_colldisn0 0.2247
|
||||||
|
tdbs 0.1565
|
||||||
|
temaas 1.1981
|
||||||
|
temasas 1.1981
|
||||||
|
temabs 1.2797
|
||||||
|
ttenas 0.4007
|
||||||
|
ttcenas 0.1727
|
||||||
|
ttaas 0.2293
|
||||||
|
ttaas_colldisn0 0.2293
|
||||||
|
ttenbs 0.6900
|
||||||
|
ttcenbs 0.1755
|
||||||
|
ttwenbs 0.0805
|
||||||
|
ttabs 0.2278
|
||||||
|
ttabs_colldisn0 0.2278
|
||||||
|
ttdbs 0.1621
|
||||||
|
tsias 0.4408
|
||||||
|
tseas 0.4408
|
||||||
|
tdftrambypas 0.6586
|
||||||
|
tdftrambypbs 0.6586
|
||||||
|
tsibs 0.1565
|
||||||
|
tsebs 0.6900
|
||||||
|
tcolldisnas 1.1981
|
||||||
|
tcolldisnbs 1.2797
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Hold time specific information.
|
||||||
|
tcenah 0.0677
|
||||||
|
tcenaf_ret1nfh 1.2585
|
||||||
|
tcenaf_ret1nrh 0.6220
|
||||||
|
taah 0.1038
|
||||||
|
taah_colldisn0 0.1038
|
||||||
|
tcenbh 0.0682
|
||||||
|
tcenbf_ret1nfh 1.2585
|
||||||
|
tcenbf_ret1nrh 0.6220
|
||||||
|
twenbh 0.2401
|
||||||
|
tabh 0.0966
|
||||||
|
tabh_colldisn0 0.0966
|
||||||
|
tdbh 0.2434
|
||||||
|
temaah 1.7699
|
||||||
|
temasah 1.7699
|
||||||
|
temabh 1.7098
|
||||||
|
ttenah 0.1142
|
||||||
|
ttcenah 0.0698
|
||||||
|
ttcenaf_ret1nfh 1.2585
|
||||||
|
ttcenaf_ret1nrh 0.6220
|
||||||
|
ttaah 0.1038
|
||||||
|
ttaah_colldisn0 0.1038
|
||||||
|
ttenbh 0.2678
|
||||||
|
ttcenbh 0.0682
|
||||||
|
ttcenbf_ret1nfh 1.2585
|
||||||
|
ttcenbf_ret1nrh 0.6220
|
||||||
|
ttwenbh 0.2417
|
||||||
|
ttabh 0.0966
|
||||||
|
ttabh_colldisn0 0.0966
|
||||||
|
ttdbh 0.2434
|
||||||
|
tret1nf_dftrambypfh 0.0439
|
||||||
|
tret1nr_dftrambypfh 1.2585
|
||||||
|
tret1nf_cenbrh 0.0439
|
||||||
|
tret1nf_cenarh 0.0432
|
||||||
|
tret1nf_tcenarh 0.0432
|
||||||
|
tret1nf_tcenbrh 0.0439
|
||||||
|
tret1nr_tcenbrh 1.2585
|
||||||
|
tret1nr_tcenarh 1.1769
|
||||||
|
tret1nr_cenbrh 1.2585
|
||||||
|
tret1nr_cenarh 1.1769
|
||||||
|
tsiah 0.0676
|
||||||
|
tseah 1.7699
|
||||||
|
tdftrambypah 1.7699
|
||||||
|
tdftrambypbh 1.2585
|
||||||
|
tdftrambypr_ret1nfh 1.2585
|
||||||
|
tdftrambypr_ret1nrh 0.6220
|
||||||
|
tsibh 0.2434
|
||||||
|
tsebh 0.2678
|
||||||
|
tcolldisnah 1.7699
|
||||||
|
tcolldisnbh 1.7098
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
|
||||||
|
icap_clka 0.0102
|
||||||
|
icap_cena 0.0019
|
||||||
|
icap_aa 0.0019
|
||||||
|
icap_clkb 0.0102
|
||||||
|
icap_cenb 0.0018
|
||||||
|
icap_wenb 0.0024
|
||||||
|
icap_ab 0.0020
|
||||||
|
icap_db 0.0024
|
||||||
|
icap_emaa 0.0075
|
||||||
|
icap_emasa 0.0030
|
||||||
|
icap_emab 0.0072
|
||||||
|
icap_tena 0.0013
|
||||||
|
icap_tcena 0.0019
|
||||||
|
icap_taa 0.0018
|
||||||
|
icap_tenb 0.0014
|
||||||
|
icap_tcenb 0.0019
|
||||||
|
icap_twenb 0.0020
|
||||||
|
icap_tab 0.0018
|
||||||
|
icap_tdb 0.0021
|
||||||
|
icap_sia 0.0018
|
||||||
|
icap_sea 0.0023
|
||||||
|
icap_dftrambyp 0.0024
|
||||||
|
icap_sib 0.0072
|
||||||
|
icap_seb 0.0022
|
||||||
|
icap_colldisn 0.0031
|
||||||
|
icap_ret1n 0.0045
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : current specific information.
|
||||||
|
icc_standby_c_chipdisable 0.013984
|
||||||
|
icc_standby_p_chipdisable 0.118912
|
||||||
|
icc_standby_c_selective_precharge 0.013711
|
||||||
|
icc_standby_p_selective_precharge 0.101339
|
||||||
|
icc_standby_c_ret1 0.013252
|
||||||
|
icc_standby_p_ret1 0.010134
|
||||||
|
icc_c_rd0_a 8.583e-05
|
||||||
|
icc_c_rd1_a 8.592e-05
|
||||||
|
icc_c_rd2_a 8.598e-05
|
||||||
|
icc_c_rd3_a 8.632e-05
|
||||||
|
icc_c_rd4_a 8.821e-05
|
||||||
|
icc_c_rd5_a 8.914e-05
|
||||||
|
icc_c_rd6_a 8.941e-05
|
||||||
|
icc_c_rd7_a 8.941e-05
|
||||||
|
icc_p_rd0_a 3.026e-03
|
||||||
|
icc_p_rd1_a 3.026e-03
|
||||||
|
icc_p_rd2_a 3.030e-03
|
||||||
|
icc_p_rd3_a 3.033e-03
|
||||||
|
icc_p_rd4_a 3.068e-03
|
||||||
|
icc_p_rd5_a 3.073e-03
|
||||||
|
icc_p_rd6_a 3.081e-03
|
||||||
|
icc_p_rd7_a 3.081e-03
|
||||||
|
icc_c_wr0_b 1.479e-04
|
||||||
|
icc_c_wr1_b 1.480e-04
|
||||||
|
icc_c_wr2_b 1.483e-04
|
||||||
|
icc_c_wr3_b 1.485e-04
|
||||||
|
icc_c_wr4_b 1.504e-04
|
||||||
|
icc_c_wr5_b 1.514e-04
|
||||||
|
icc_c_wr6_b 1.517e-04
|
||||||
|
icc_c_wr7_b 1.517e-04
|
||||||
|
icc_p_wr0_b 4.185e-03
|
||||||
|
icc_p_wr1_b 4.185e-03
|
||||||
|
icc_p_wr2_b 4.189e-03
|
||||||
|
icc_p_wr3_b 4.192e-03
|
||||||
|
icc_p_wr4_b 4.226e-03
|
||||||
|
icc_p_wr5_b 4.232e-03
|
||||||
|
icc_p_wr6_b 4.239e-03
|
||||||
|
icc_p_wr7_b 4.239e-03
|
||||||
|
icc_c_desela 0.000e+00
|
||||||
|
icc_p_desela 4.035e-05
|
||||||
|
icc_c_deselb 0.000e+00
|
||||||
|
icc_p_deselb 9.960e-04
|
||||||
|
icc_c_peak 2.22663
|
||||||
|
icc_p_peak 24.239074
|
||||||
|
icc_c_inrush 1.225138
|
||||||
|
icc_p_inrush 23.084833
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,162 @@
|
|||||||
|
#
|
||||||
|
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||||
|
#
|
||||||
|
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||||
|
#
|
||||||
|
# Use of this Software is subject to the terms and conditions of the
|
||||||
|
# applicable license agreement with ARM Physical IP, Inc.
|
||||||
|
# In addition, this Software is protected by patents, copyright law
|
||||||
|
# and international treaties.
|
||||||
|
#
|
||||||
|
# The copyright notice(s) in this Software does not indicate actual or
|
||||||
|
# intended publication of this Software.
|
||||||
|
#
|
||||||
|
# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
|
||||||
|
#
|
||||||
|
# Creation Date: Sun Oct 13 11:08:16 2019
|
||||||
|
#
|
||||||
|
# Instance Options:
|
||||||
|
# Instance Name: rf2_32x128_wm1
|
||||||
|
# Number of Words: 32
|
||||||
|
# Number of Bits: 128
|
||||||
|
# Multiplexer Width: 2
|
||||||
|
# Multi-Vt selection: LL
|
||||||
|
# Frequency <MHz>: 1
|
||||||
|
# Activity Factor <%>: 50
|
||||||
|
# Pipeline: off
|
||||||
|
# Word-Write Mask: on
|
||||||
|
# Word Partition Size: 1
|
||||||
|
# Write through: off
|
||||||
|
# Top Metal Layer: m5-m10
|
||||||
|
# Power Type: otc
|
||||||
|
# Redundancy: off
|
||||||
|
# Redundant Columns: 2
|
||||||
|
# Redundant Rows: 0
|
||||||
|
# BIST MUXes: on
|
||||||
|
# Soft Error Repair (SER): none
|
||||||
|
# Power Gating: off
|
||||||
|
# Back Biasing: off
|
||||||
|
# Retention: on
|
||||||
|
# Extra Margin Adjustment: on
|
||||||
|
# Advanced Test Features: off
|
||||||
|
# Customer Comment: This is a memory instance
|
||||||
|
# Bus-notation: on
|
||||||
|
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||||
|
# Name Case: upper
|
||||||
|
# Check Instance Name: on
|
||||||
|
# Diodes: on
|
||||||
|
# Drive Strength: 6
|
||||||
|
# Site Definitions: off
|
||||||
|
# Library Name: USERLIB
|
||||||
|
# Liberty setting: nldm
|
||||||
|
#
|
||||||
|
# Compiler Versions:
|
||||||
|
# Memory Version: r0p0
|
||||||
|
# Lang compiler Version: 4.5.1-EAC
|
||||||
|
# View Name: avm
|
||||||
|
# AMCI Version: 2.0.4-EAC
|
||||||
|
# avm_memcomp Version: 2.3.7-EAC
|
||||||
|
#
|
||||||
|
# Modeling Assumptions: N/A
|
||||||
|
#
|
||||||
|
# Modeling Limitations: N/A
|
||||||
|
#
|
||||||
|
# Known Bugs: N/A
|
||||||
|
#
|
||||||
|
# Known Work Arounds: N/A
|
||||||
|
#
|
||||||
|
rf2_32x128_wm1 {
|
||||||
|
MEMORY_TYPE RegFile
|
||||||
|
EQUIV_GATE_COUNT 4506
|
||||||
|
VDD_PIN VDDCE VDDPE
|
||||||
|
GND_PIN VSSE
|
||||||
|
#This file is for PROCESS TT, CORNER TT_0P81V_0P81V_0C
|
||||||
|
#However, RedHawk needs the process to be specified as 'PROCESS XX'
|
||||||
|
PROCESS XX
|
||||||
|
Cload 3.5e-05nF
|
||||||
|
VDD 0.81 0.81
|
||||||
|
|
||||||
|
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
|
||||||
|
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
|
||||||
|
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||||
|
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
|
||||||
|
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||||
|
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
|
||||||
|
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
|
||||||
|
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
|
||||||
|
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
|
||||||
|
|
||||||
|
Cpd avm_into_lowpwr {
|
||||||
|
VDDCE VSSE 5.49122e-05nF
|
||||||
|
VDDPE VSSE 6.03933e-04nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_into_lowpwr {
|
||||||
|
VDDCE VSSE 0.99817mA
|
||||||
|
VDDPE VSSE 4.32165mA
|
||||||
|
}
|
||||||
|
Cpd avm_outof_lowpwr {
|
||||||
|
VDDCE VSSE 6.04034e-05nF
|
||||||
|
VDDPE VSSE 5.53994e-03nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_outof_lowpwr {
|
||||||
|
VDDCE VSSE 1.09799mA
|
||||||
|
VDDPE VSSE 27.14816mA
|
||||||
|
}
|
||||||
|
Cpd avm_read_write {
|
||||||
|
VDDCE VSSE 2.78800e-04nF
|
||||||
|
VDDPE VSSE 8.57721e-03nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_read_write {
|
||||||
|
VDDCE VSSE 2.22663mA
|
||||||
|
VDDPE VSSE 28.41823mA
|
||||||
|
}
|
||||||
|
Cpd avm_read_desel {
|
||||||
|
VDDCE VSSE 1.02471e-04nF
|
||||||
|
VDDPE VSSE 3.60089e-03nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_read_desel {
|
||||||
|
VDDCE VSSE 1.06930mA
|
||||||
|
VDDPE VSSE 12.67500mA
|
||||||
|
}
|
||||||
|
Cpd avm_desel_write {
|
||||||
|
VDDCE VSSE 1.76329e-04nF
|
||||||
|
VDDPE VSSE 4.97632e-03nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_desel_write {
|
||||||
|
VDDCE VSSE 1.19590mA
|
||||||
|
VDDPE VSSE 16.68900mA
|
||||||
|
}
|
||||||
|
Cpd avm_scan_capture {
|
||||||
|
VDDCE VSSE 9.45361e-06nF
|
||||||
|
VDDPE VSSE 1.09603e-02nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_scan_capture {
|
||||||
|
VDDCE VSSE 0.18935mA
|
||||||
|
VDDPE VSSE 15.78165mA
|
||||||
|
}
|
||||||
|
Cpd avm_scan_shift {
|
||||||
|
VDDCE VSSE 9.45361e-06nF
|
||||||
|
VDDPE VSSE 1.09603e-02nF
|
||||||
|
}
|
||||||
|
PEAK_I avm_scan_shift {
|
||||||
|
VDDCE VSSE 0.18935mA
|
||||||
|
VDDPE VSSE 15.78165mA
|
||||||
|
}
|
||||||
|
Cpd standby_trig {
|
||||||
|
VDDCE VSSE 0.00000e+00nF
|
||||||
|
VDDPE VSSE 2.47655e-06nF
|
||||||
|
}
|
||||||
|
Cpd standby_ntrig {
|
||||||
|
VDDCE VSSE 0.00000e+00nF
|
||||||
|
VDDPE VSSE 2.17055e-05nF
|
||||||
|
}
|
||||||
|
LEAKAGE_I {
|
||||||
|
VDDCE VSSE 6.55600e-04mA
|
||||||
|
VDDPE VSSE 4.40600e-03mA
|
||||||
|
}
|
||||||
|
tsu 0.14063ns
|
||||||
|
ck2q_delay 0.664619ns
|
||||||
|
tr_q 0.020317ns
|
||||||
|
tf_q 0.023075ns
|
||||||
|
CHARACTERIZATION_MODE accurate
|
||||||
|
}
|
||||||
@@ -0,0 +1,342 @@
|
|||||||
|
#
|
||||||
|
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||||
|
#
|
||||||
|
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||||
|
#
|
||||||
|
# Use of this Software is subject to the terms and conditions of the
|
||||||
|
# applicable license agreement with ARM Physical IP, Inc.
|
||||||
|
# In addition, this Software is protected by patents, copyright law
|
||||||
|
# and international treaties.
|
||||||
|
#
|
||||||
|
# The copyright notice(s) in this Software does not indicate actual or
|
||||||
|
# intended publication of this Software.
|
||||||
|
#
|
||||||
|
# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
|
||||||
|
#
|
||||||
|
# Creation Date: Sun Oct 13 11:08:40 2019
|
||||||
|
#
|
||||||
|
# Instance Options:
|
||||||
|
# Instance Name: rf2_32x128_wm1
|
||||||
|
# Number of Words: 32
|
||||||
|
# Number of Bits: 128
|
||||||
|
# Multiplexer Width: 2
|
||||||
|
# Multi-Vt selection: LL
|
||||||
|
# Frequency <MHz>: 1
|
||||||
|
# Activity Factor <%>: 50
|
||||||
|
# Pipeline: off
|
||||||
|
# Word-Write Mask: on
|
||||||
|
# Word Partition Size: 1
|
||||||
|
# Write through: off
|
||||||
|
# Top Metal Layer: m5-m10
|
||||||
|
# Power Type: otc
|
||||||
|
# Redundancy: off
|
||||||
|
# Redundant Columns: 2
|
||||||
|
# Redundant Rows: 0
|
||||||
|
# BIST MUXes: on
|
||||||
|
# Soft Error Repair (SER): none
|
||||||
|
# Power Gating: off
|
||||||
|
# Back Biasing: off
|
||||||
|
# Retention: on
|
||||||
|
# Extra Margin Adjustment: on
|
||||||
|
# Advanced Test Features: off
|
||||||
|
# Customer Comment: This is a memory instance
|
||||||
|
# Bus-notation: on
|
||||||
|
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||||
|
# Name Case: upper
|
||||||
|
# Check Instance Name: on
|
||||||
|
# Diodes: on
|
||||||
|
# Drive Strength: 6
|
||||||
|
# Site Definitions: off
|
||||||
|
# Library Name: USERLIB
|
||||||
|
# Liberty setting: nldm
|
||||||
|
#
|
||||||
|
# Compiler Versions:
|
||||||
|
# Memory Version: r0p0
|
||||||
|
# Lang compiler Version: 4.5.1-EAC
|
||||||
|
# View Name: datatable
|
||||||
|
# AMCI Version: 2.0.4-EAC
|
||||||
|
# datatable_memcomp Version: 2.3.2-EAC
|
||||||
|
#
|
||||||
|
# Modeling Assumptions: N/A
|
||||||
|
#
|
||||||
|
# Modeling Limitations: N/A
|
||||||
|
#
|
||||||
|
# Known Bugs: N/A
|
||||||
|
#
|
||||||
|
# Known Work Arounds: N/A
|
||||||
|
#
|
||||||
|
# Units used in Datatable :
|
||||||
|
# geomx: micron
|
||||||
|
# geomy: micron
|
||||||
|
# Voltage: volts
|
||||||
|
# Temprature: Degree Celsius
|
||||||
|
# Current: mA
|
||||||
|
# Time: ns
|
||||||
|
#
|
||||||
|
name tt_0p81v_0p81v_0c
|
||||||
|
S N
|
||||||
|
geomx 21.9750
|
||||||
|
geomy 414.8600
|
||||||
|
volt 0.8100
|
||||||
|
temp 0.0000
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
|
||||||
|
tcenacenya 0.1433
|
||||||
|
ttcenacenya 0.1430
|
||||||
|
ttenacenyapu 0.1952
|
||||||
|
ttenacenyanu 0.2353
|
||||||
|
tdftrambypcenya 0.2564
|
||||||
|
taaaya 0.1269
|
||||||
|
ttaaaya 0.1283
|
||||||
|
ttenaayapu 0.2365
|
||||||
|
ttenaayanu 0.2267
|
||||||
|
tdftrambypaya 0.2371
|
||||||
|
tcenbcenyb 0.1457
|
||||||
|
ttcenbcenyb 0.1462
|
||||||
|
ttenbcenybpu 0.2034
|
||||||
|
ttenbcenybnu 0.3394
|
||||||
|
tdftrambypcenyb 0.2475
|
||||||
|
twenbwenyb 0.1742
|
||||||
|
ttwenbwenyb 0.1735
|
||||||
|
ttenbwenybpu 0.4697
|
||||||
|
ttenbwenybnu 0.4927
|
||||||
|
tdftrambypwenyb 0.2830
|
||||||
|
tabayb 0.1276
|
||||||
|
ttabayb 0.1297
|
||||||
|
ttenbaybpu 0.3547
|
||||||
|
ttenbaybnu 0.3445
|
||||||
|
tdftrambypayb 0.2336
|
||||||
|
taccqa_rd0 0.6615
|
||||||
|
taccqa_rd1 0.6619
|
||||||
|
taccqa_rd2 0.6621
|
||||||
|
taccqa_rd3 0.6646
|
||||||
|
taccqa_rd4 0.7426
|
||||||
|
taccqa_rd5 0.8087
|
||||||
|
taccqa_rd6 0.8845
|
||||||
|
taccqa_rd7 0.9511
|
||||||
|
taccqa_scan0 0.6615
|
||||||
|
taccqa_scan1 0.6619
|
||||||
|
taccqa_scan2 0.6621
|
||||||
|
taccqa_scan3 0.6646
|
||||||
|
taccqa_scan4 0.7426
|
||||||
|
taccqa_scan5 0.8087
|
||||||
|
taccqa_scan6 0.8845
|
||||||
|
taccqa_scan7 0.9511
|
||||||
|
tclkasoa_rd0 0.7081
|
||||||
|
tclkasoa_rd1 0.7086
|
||||||
|
tclkasoa_rd2 0.7088
|
||||||
|
tclkasoa_rd3 0.7113
|
||||||
|
tclkasoa_rd4 0.7893
|
||||||
|
tclkasoa_rd5 0.8553
|
||||||
|
tclkasoa_rd6 0.9312
|
||||||
|
tclkasoa_rd7 0.9977
|
||||||
|
tclkasoa_scan0 0.7081
|
||||||
|
tclkasoa_scan1 0.7086
|
||||||
|
tclkasoa_scan2 0.7088
|
||||||
|
tclkasoa_scan3 0.7113
|
||||||
|
tclkasoa_scan4 0.7893
|
||||||
|
tclkasoa_scan5 0.8553
|
||||||
|
tclkasoa_scan6 0.9312
|
||||||
|
tclkasoa_scan7 0.9977
|
||||||
|
tclkbsob 0.3685
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Kload specific information.
|
||||||
|
kload_cenya 2.6704
|
||||||
|
kload_aya 2.2063
|
||||||
|
kload_cenyb 2.6149
|
||||||
|
kload_wenyb 2.2794
|
||||||
|
kload_ayb 2.1961
|
||||||
|
kload_qa 0.8471
|
||||||
|
kload_soa 2.1164
|
||||||
|
kload_sob 2.2664
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Cycle time specific information.
|
||||||
|
tcyca_ema0 0.9659
|
||||||
|
tcyca_ema1 0.9664
|
||||||
|
tcyca_ema2 0.9666
|
||||||
|
tcyca_ema3 0.9691
|
||||||
|
tcyca_ema4 1.0475
|
||||||
|
tcyca_ema5 1.1139
|
||||||
|
tcyca_ema6 1.1902
|
||||||
|
tcyca_ema7 1.2570
|
||||||
|
tcycb_ema0 0.9854
|
||||||
|
tcycb_ema1 0.9917
|
||||||
|
tcycb_ema2 0.9985
|
||||||
|
tcycb_ema3 1.0071
|
||||||
|
tcycb_ema4 1.0985
|
||||||
|
tcycb_ema5 1.1649
|
||||||
|
tcycb_ema6 1.2553
|
||||||
|
tcycb_ema7 1.3232
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Clock collision specific information.
|
||||||
|
tcracwb_rd0 0.5646
|
||||||
|
tcracwb_rd1 0.5651
|
||||||
|
tcracwb_rd2 0.5653
|
||||||
|
tcracwb_rd3 0.5678
|
||||||
|
tcracwb_rd4 0.6457
|
||||||
|
tcracwb_rd5 0.7116
|
||||||
|
tcracwb_rd6 0.7874
|
||||||
|
tcracwb_rd7 0.8538
|
||||||
|
tcwbcra_wr0 0.8095
|
||||||
|
tcwbcra_wr1 0.8158
|
||||||
|
tcwbcra_wr2 0.8225
|
||||||
|
tcwbcra_wr3 0.8311
|
||||||
|
tcwbcra_wr4 0.9219
|
||||||
|
tcwbcra_wr5 0.9878
|
||||||
|
tcwbcra_wr6 1.0776
|
||||||
|
tcwbcra_wr7 1.1450
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Pulse width specific information.
|
||||||
|
tckah 0.1491
|
||||||
|
tckal 0.1500
|
||||||
|
tckbh 0.1494
|
||||||
|
tckbl 0.1495
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Setup time specific information.
|
||||||
|
tcenas 0.1484
|
||||||
|
taas 0.1785
|
||||||
|
taas_colldisn0 0.1785
|
||||||
|
tcenbs 0.1506
|
||||||
|
twenbs 0.0379
|
||||||
|
tabs 0.1805
|
||||||
|
tabs_colldisn0 0.1805
|
||||||
|
tdbs 0.0998
|
||||||
|
temaas 1.0198
|
||||||
|
temasas 1.0198
|
||||||
|
temabs 1.0578
|
||||||
|
ttenas 0.3071
|
||||||
|
ttcenas 0.1484
|
||||||
|
ttaas 0.1798
|
||||||
|
ttaas_colldisn0 0.1798
|
||||||
|
ttenbs 0.6165
|
||||||
|
ttcenbs 0.1507
|
||||||
|
ttwenbs 0.0379
|
||||||
|
ttabs 0.1825
|
||||||
|
ttabs_colldisn0 0.1825
|
||||||
|
ttdbs 0.1050
|
||||||
|
tsias 0.3379
|
||||||
|
tseas 0.3379
|
||||||
|
tdftrambypas 0.4451
|
||||||
|
tdftrambypbs 0.4451
|
||||||
|
tsibs 0.0998
|
||||||
|
tsebs 0.6165
|
||||||
|
tcolldisnas 1.0198
|
||||||
|
tcolldisnbs 1.0578
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Hold time specific information.
|
||||||
|
tcenah 0.0580
|
||||||
|
tcenaf_ret1nfh 1.0426
|
||||||
|
tcenaf_ret1nrh 0.5141
|
||||||
|
taah 0.0896
|
||||||
|
taah_colldisn0 0.0896
|
||||||
|
tcenbh 0.0589
|
||||||
|
tcenbf_ret1nfh 1.0426
|
||||||
|
tcenbf_ret1nrh 0.5141
|
||||||
|
twenbh 0.2220
|
||||||
|
tabh 0.0853
|
||||||
|
tabh_colldisn0 0.0853
|
||||||
|
tdbh 0.2104
|
||||||
|
temaah 1.4044
|
||||||
|
temasah 1.4044
|
||||||
|
temabh 1.3586
|
||||||
|
ttenah 0.0986
|
||||||
|
ttcenah 0.0588
|
||||||
|
ttcenaf_ret1nfh 1.0426
|
||||||
|
ttcenaf_ret1nrh 0.5141
|
||||||
|
ttaah 0.0896
|
||||||
|
ttaah_colldisn0 0.0896
|
||||||
|
ttenbh 0.2462
|
||||||
|
ttcenbh 0.0595
|
||||||
|
ttcenbf_ret1nfh 1.0426
|
||||||
|
ttcenbf_ret1nrh 0.5141
|
||||||
|
ttwenbh 0.2238
|
||||||
|
ttabh 0.0853
|
||||||
|
ttabh_colldisn0 0.0853
|
||||||
|
ttdbh 0.2104
|
||||||
|
tret1nf_dftrambypfh 0.0377
|
||||||
|
tret1nr_dftrambypfh 1.0426
|
||||||
|
tret1nf_cenbrh 0.0377
|
||||||
|
tret1nf_cenarh 0.0371
|
||||||
|
tret1nf_tcenarh 0.0371
|
||||||
|
tret1nf_tcenbrh 0.0377
|
||||||
|
tret1nr_tcenbrh 1.0426
|
||||||
|
tret1nr_tcenarh 1.0045
|
||||||
|
tret1nr_cenbrh 1.0426
|
||||||
|
tret1nr_cenarh 1.0045
|
||||||
|
tsiah 0.0946
|
||||||
|
tseah 1.4044
|
||||||
|
tdftrambypah 1.4044
|
||||||
|
tdftrambypbh 1.0426
|
||||||
|
tdftrambypr_ret1nfh 1.0426
|
||||||
|
tdftrambypr_ret1nrh 0.5141
|
||||||
|
tsibh 0.2104
|
||||||
|
tsebh 0.2462
|
||||||
|
tcolldisnah 1.4044
|
||||||
|
tcolldisnbh 1.3586
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
|
||||||
|
icap_clka 0.0093
|
||||||
|
icap_cena 0.0015
|
||||||
|
icap_aa 0.0016
|
||||||
|
icap_clkb 0.0093
|
||||||
|
icap_cenb 0.0016
|
||||||
|
icap_wenb 0.0019
|
||||||
|
icap_ab 0.0016
|
||||||
|
icap_db 0.0019
|
||||||
|
icap_emaa 0.0059
|
||||||
|
icap_emasa 0.0024
|
||||||
|
icap_emab 0.0057
|
||||||
|
icap_tena 0.0011
|
||||||
|
icap_tcena 0.0016
|
||||||
|
icap_taa 0.0015
|
||||||
|
icap_tenb 0.0011
|
||||||
|
icap_tcenb 0.0017
|
||||||
|
icap_twenb 0.0016
|
||||||
|
icap_tab 0.0016
|
||||||
|
icap_tdb 0.0017
|
||||||
|
icap_sia 0.0014
|
||||||
|
icap_sea 0.0018
|
||||||
|
icap_dftrambyp 0.0020
|
||||||
|
icap_sib 0.0054
|
||||||
|
icap_seb 0.0019
|
||||||
|
icap_colldisn 0.0024
|
||||||
|
icap_ret1n 0.0037
|
||||||
|
# High Capacity Two Port Register File SVT MVT Compiler : current specific information.
|
||||||
|
icc_standby_c_chipdisable 6.556e-04
|
||||||
|
icc_standby_p_chipdisable 4.406e-03
|
||||||
|
icc_standby_c_selective_precharge 6.469e-04
|
||||||
|
icc_standby_p_selective_precharge 3.724e-03
|
||||||
|
icc_standby_c_ret1 6.357e-04
|
||||||
|
icc_standby_p_ret1 3.724e-04
|
||||||
|
icc_c_rd0_a 8.253e-05
|
||||||
|
icc_c_rd1_a 8.261e-05
|
||||||
|
icc_c_rd2_a 8.267e-05
|
||||||
|
icc_c_rd3_a 8.300e-05
|
||||||
|
icc_c_rd4_a 8.482e-05
|
||||||
|
icc_c_rd5_a 8.572e-05
|
||||||
|
icc_c_rd6_a 8.597e-05
|
||||||
|
icc_c_rd7_a 8.597e-05
|
||||||
|
icc_p_rd0_a 2.910e-03
|
||||||
|
icc_p_rd1_a 2.910e-03
|
||||||
|
icc_p_rd2_a 2.914e-03
|
||||||
|
icc_p_rd3_a 2.917e-03
|
||||||
|
icc_p_rd4_a 2.950e-03
|
||||||
|
icc_p_rd5_a 2.955e-03
|
||||||
|
icc_p_rd6_a 2.962e-03
|
||||||
|
icc_p_rd7_a 2.962e-03
|
||||||
|
icc_c_wr0_b 1.422e-04
|
||||||
|
icc_c_wr1_b 1.423e-04
|
||||||
|
icc_c_wr2_b 1.426e-04
|
||||||
|
icc_c_wr3_b 1.428e-04
|
||||||
|
icc_c_wr4_b 1.446e-04
|
||||||
|
icc_c_wr5_b 1.455e-04
|
||||||
|
icc_c_wr6_b 1.459e-04
|
||||||
|
icc_c_wr7_b 1.459e-04
|
||||||
|
icc_p_wr0_b 4.024e-03
|
||||||
|
icc_p_wr1_b 4.024e-03
|
||||||
|
icc_p_wr2_b 4.028e-03
|
||||||
|
icc_p_wr3_b 4.031e-03
|
||||||
|
icc_p_wr4_b 4.064e-03
|
||||||
|
icc_p_wr5_b 4.069e-03
|
||||||
|
icc_p_wr6_b 4.076e-03
|
||||||
|
icc_p_wr7_b 4.076e-03
|
||||||
|
icc_c_desela 0.000e+00
|
||||||
|
icc_p_desela 3.884e-05
|
||||||
|
icc_c_deselb 0.000e+00
|
||||||
|
icc_p_deselb 9.578e-04
|
||||||
|
icc_c_peak 2.22663
|
||||||
|
icc_p_peak 28.418225
|
||||||
|
icc_c_inrush 1.436369
|
||||||
|
icc_p_inrush 27.064976
|
||||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user