arbiter specialization
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Blaise Tine
@@ -1,71 +1,88 @@
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`include "VX_platform.vh"
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// Fast encoder using parallel prefix computation
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// Adapter from BaseJump STL: http://bjump.org/index.html
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// Adapter from BaseJump STL: http://bjump.org/data_out.html
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module VX_onehot_encoder #(
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parameter N = 1,
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parameter REVERSE = 0,
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parameter FAST = 1
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parameter N = 1,
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parameter LN = `LOG2UP(N)
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) (
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input wire [N-1:0] data_in,
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output wire [`LOG2UP(N)-1:0] data_out,
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output wire valid
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input wire [N-1:0] data_in,
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output wire [LN-1:0] data_out,
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output wire valid
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);
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if (FAST) begin
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`IGNORE_WARNINGS_BEGIN
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localparam levels_lp = $clog2(N);
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localparam aligned_width_lp = 1 << $clog2(N);
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wire [levels_lp:0][aligned_width_lp-1:0] addr;
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wire [levels_lp:0][aligned_width_lp-1:0] v;
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// base case, also handle padding for non-power of two inputs
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assign v[0] = REVERSE ? (data_in << (aligned_width_lp - N)) : ((aligned_width_lp)'(data_in));
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assign addr[0] = 'x;
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for (genvar level = 1; level < levels_lp+1; level=level+1) begin
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localparam segments_lp = 2**(levels_lp-level);
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localparam segment_slot_lp = aligned_width_lp/segments_lp;
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localparam segment_width_lp = level; // how many bits are needed at each level
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for (genvar segment = 0; segment < segments_lp; segment=segment+1) begin
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wire [1:0] vs = {
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v[level-1][segment*segment_slot_lp+(segment_slot_lp >> 1)],
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v[level-1][segment*segment_slot_lp]
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};
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assign v[level][segment*segment_slot_lp] = (| vs);
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if (N == 1) begin
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assign data_out = data_in;
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assign valid = data_in;
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end else if (N == 2) begin
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assign data_out = data_in[1];
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assign valid = (| data_in);
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if (level == 1) begin
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assign addr[level][(segment*segment_slot_lp)+:segment_width_lp] = vs[!REVERSE];
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end else begin
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assign addr[level][(segment*segment_slot_lp)+:segment_width_lp] = {
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vs[!REVERSE],
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addr[level-1][segment*segment_slot_lp+:segment_width_lp-1] | addr[level-1][segment*segment_slot_lp+(segment_slot_lp >> 1)+:segment_width_lp-1]
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};
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end
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end
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end
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assign data_out = addr[levels_lp][`LOG2UP(N)-1:0];
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assign valid = v[levels_lp][0];
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`IGNORE_WARNINGS_END
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end else begin
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reg [LN-1:0] index_r;
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reg [`LOG2UP(N)-1:0] data_out_r;
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reg valid_r;
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always @(*) begin
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data_out_r = 'x;
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for (integer i = 0; i < N; i++) begin
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if (data_in[i]) begin
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data_out_r = `LOG2UP(N)'(i);
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if (N == 4) begin
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always @(*) begin
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casez (data_in)
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4'b0001: index_r = LN'(0);
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4'b001?: index_r = LN'(1);
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4'b01??: index_r = LN'(2);
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4'b1???: index_r = LN'(3);
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default: index_r = 'x;
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endcase
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end
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end else if (N == 8) begin
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always @(*) begin
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casez (data_in)
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8'b00000001: index_r = LN'(0);
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8'b0000001?: index_r = LN'(1);
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8'b000001??: index_r = LN'(2);
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8'b00001???: index_r = LN'(3);
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8'b0001????: index_r = LN'(4);
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8'b001?????: index_r = LN'(5);
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8'b01??????: index_r = LN'(6);
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8'b1???????: index_r = LN'(7);
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default: index_r = 'x;
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endcase
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end
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end else if (N == 16) begin
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always @(*) begin
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casez (data_in)
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16'b0000000000000001: index_r = LN'(0);
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16'b000000000000001?: index_r = LN'(1);
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16'b00000000000001??: index_r = LN'(2);
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16'b0000000000001???: index_r = LN'(3);
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16'b000000000001????: index_r = LN'(4);
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16'b00000000001?????: index_r = LN'(5);
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16'b0000000001??????: index_r = LN'(6);
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16'b000000001???????: index_r = LN'(7);
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16'b00000001????????: index_r = LN'(8);
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16'b0000001?????????: index_r = LN'(9);
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16'b000001??????????: index_r = LN'(10);
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16'b00001???????????: index_r = LN'(11);
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16'b0001????????????: index_r = LN'(12);
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16'b001?????????????: index_r = LN'(13);
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16'b01??????????????: index_r = LN'(14);
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16'b1???????????????: index_r = LN'(15);
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default: index_r = 'x;
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endcase
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end
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end else begin
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always @(*) begin
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index_r = 'x;
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for (integer i = 0; i < N; i++) begin
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if (data_in[i]) begin
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index_r = `LOG2UP(N)'(i);
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end
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end
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end
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end
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assign data_out = data_out_r;
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assign data_out = index_r;
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assign valid = (| data_in);
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end
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