gpr pipeline optimization

hw/rtl/fp_cores/VX_fp_fpga.v

@@ -38,8 +38,8 @@ module VX_fp_fpga (
     
     VX_fpnew #(
         .FMULADD  (0),
-        .FDIVSQRT (1),
-        .FNONCOMP (1),
+        .FDIVSQRT (0),
+        .FNONCOMP (0),
         .FCONV    (1)
     ) fp_core (
         .clk        (clk),
@@ -67,13 +67,15 @@ module VX_fp_fpga (
         .out_valid  (fpnew_out_valid)
     );
 
-    acl_fp_add fp_add (
-        .clock  (clk), 
-        .dataa  (dataa), 
-        .datab  (datab),         
-        .enable (add_out_ready), 
-        .result (add_result)
-    );
+    for (i = 0; i < `NUM_THREADS; i++) begin
+        acl_fp_add fp_add (
+            .clock  (clk), 
+            .dataa  (dataa), 
+            .datab  (datab),         
+            .enable (add_out_ready), 
+            .result (add_result[i])
+        );
+    end
 
     assign in_reqady  = fpnew_in_ready;
     assign has_fflags = fpnew_has_fflags;  
@@ -81,6 +83,8 @@ module VX_fp_fpga (
     assign out_tag    = fpnew_out_tag;
     assign fpnew_out_ready = out_ready;
 
+    assign add_out_ready = out_ready;
+
     assign result = fpnew_out_valid ? fpnew_result : add_result;
     assign out_valid = fpnew_out_valid; 
 

hw/rtl/fp_cores/VX_fpnew.v

@@ -66,7 +66,7 @@ module VX_fpnew #(
     wire fpu_in_ready, fpu_in_valid;    
     wire fpu_out_ready, fpu_out_valid;
 
-    reg [`LOG2UP(`FPURQ_SIZE)-1:0] fpu_in_tag, fpu_out_tag;
+    reg [`ISTAG_BITS-1:0] fpu_in_tag, fpu_out_tag;
     
     reg [2:0][`NUM_THREADS-1:0][31:0] fpu_operands;   
     
@@ -138,7 +138,7 @@ module VX_fpnew #(
             fpnew_top #( 
                 .Features       (FPU_FEATURES),
                 .Implementation (FPU_IMPLEMENTATION),
-                .TagType        (logic[`LOG2UP(`FPURQ_SIZE)+1+1-1:0])
+                .TagType        (logic[`ISTAG_BITS+1+1-1:0])
             ) fpnew_core (
                 .clk_i          (clk),
                 .rst_ni         (1'b1),