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gpr pipeline optimization

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This commit is contained in:
Blaise Tine
2020-08-01 12:38:30 -04:00
parent 31ee824862
commit b8cd3b0b28
17 changed files with 121 additions and 140 deletions
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22
hw/rtl/VX_gpr_ram.v
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@@ -3,26 +3,28 @@
module VX_gpr_ram (
input wire clk,
input wire [`NUM_THREADS-1:0] we,
input wire [`NR_BITS-1:0] waddr,
input wire [`NW_BITS+`NR_BITS-1:0] waddr,
input wire [`NUM_THREADS-1:0][31:0] wdata,
input wire [`NR_BITS-1:0] rs1,
input wire [`NR_BITS-1:0] rs2,
input wire [`NW_BITS+`NR_BITS-1:0] rs1,
input wire [`NW_BITS+`NR_BITS-1:0] rs2,
output wire [`NUM_THREADS-1:0][31:0] rs1_data,
output wire [`NUM_THREADS-1:0][31:0] rs2_data
);
`ifndef ASIC
reg [`NUM_THREADS-1:0][3:0][7:0] ram [`NUM_REGS-1:0];
reg [`NUM_THREADS-1:0][3:0][7:0] ram [(`NUM_WARPS * `NUM_REGS)-1:0];
integer i;
integer i, j;
initial begin
// initialize r0 to 0
for (i = 0; i < `NUM_THREADS; i++) begin
ram[0][i][0] = 0;
ram[0][i][1] = 0;
ram[0][i][2] = 0;
ram[0][i][3] = 0;
for (j = 0; j < `NUM_WARPS; j++) begin
for (i = 0; i < `NUM_THREADS; i++) begin
ram[j * `NUM_REGS][i][0] = 8'h0;
ram[j * `NUM_REGS][i][1] = 8'h0;
ram[j * `NUM_REGS][i][2] = 8'h0;
ram[j * `NUM_REGS][i][3] = 8'h0;
end
end
end