gpr pipeline optimization

hw/rtl/VX_gpr_fp_ctrl.v

@@ -10,7 +10,7 @@ module VX_gpr_fp_ctrl (
 	input wire [`NUM_THREADS-1:0][31:0] rs2_data,
 
 	// outputs 
-	output wire [`NR_BITS-1:0]	raddr1,               
+	output wire [`NW_BITS+`NR_BITS-1:0]	raddr1,               
 
 	VX_gpr_read_if	gpr_read_if
 );
@@ -18,32 +18,30 @@ module VX_gpr_fp_ctrl (
     reg [`NUM_THREADS-1:0][31:0] tmp_rs1_data;
 	reg read_rs3;
 
-	wire gpr_delay = gpr_read_if.valid && gpr_read_if.use_rs3 && ~read_rs3;
+	wire delay = gpr_read_if.valid && gpr_read_if.use_rs3 && ~read_rs3;
 
-	wire gpr_fire = gpr_read_if.valid && gpr_read_if.ready;
+	wire read_fire = gpr_read_if.valid && gpr_read_if.out_ready;
 
 	always @(posedge clk) begin
 		if (reset) begin
 			read_rs3 <= 0;
-        end else if (gpr_delay) begin
+        end else if (delay) begin
 			read_rs3 <= 1;
-        end else if (gpr_fire) begin
+        end else if (read_fire) begin
 			read_rs3 <= 0;
         end
 	end
 
     // backup original rs1 data
 	always @(posedge clk) begin	
-		if (gpr_delay) begin
+		if (delay) begin
 			tmp_rs1_data <= rs1_data;
 		end
 	end
 
 	// outputs
-
-	assign raddr1 = read_rs3 ? gpr_read_if.rs3 : gpr_read_if.rs1;
-
-    assign gpr_read_if.ready    = ~gpr_delay;
+	assign raddr1 = {gpr_read_if.warp_num, (read_rs3 ? gpr_read_if.rs3 : gpr_read_if.rs1)};
+    assign gpr_read_if.in_ready = ~delay;
 	assign gpr_read_if.rs1_data = gpr_read_if.use_rs3 ? tmp_rs1_data : rs1_data;
     assign gpr_read_if.rs2_data = rs2_data;
     assign gpr_read_if.rs3_data = rs1_data;