From b8022822bbd129708932f733388fa0fde3eba03d Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 18 Mar 2021 14:28:58 -0400 Subject: [PATCH] minor update --- hw/rtl/VX_databus_arb.v | 118 --------------------------------- hw/rtl/VX_dcache_arb.v | 118 --------------------------------- hw/rtl/VX_tex_cache_arb.v | 136 -------------------------------------- 3 files changed, 372 deletions(-) delete mode 100644 hw/rtl/VX_databus_arb.v delete mode 100644 hw/rtl/VX_dcache_arb.v delete mode 100644 hw/rtl/VX_tex_cache_arb.v diff --git a/hw/rtl/VX_databus_arb.v b/hw/rtl/VX_databus_arb.v deleted file mode 100644 index df5ac42a..00000000 --- a/hw/rtl/VX_databus_arb.v +++ /dev/null @@ -1,118 +0,0 @@ -`include "VX_define.vh" - -module VX_databus_arb ( - input wire clk, - input wire reset, - - // input request - VX_dcache_core_req_if core_req_if, - - // output requests - VX_dcache_core_req_if cache_req_if, - VX_dcache_core_req_if smem_req_if, - - // input responses - VX_dcache_core_rsp_if cache_rsp_if, - VX_dcache_core_rsp_if smem_rsp_if, - - // output response - VX_dcache_core_rsp_if core_rsp_if -); - localparam SMEM_ASHIFT = `CLOG2(`SHARED_MEM_BASE_ADDR_ALIGN); - localparam REQ_ASHIFT = `CLOG2(`DWORD_SIZE); - localparam REQ_ADDRW = 32 - REQ_ASHIFT; - localparam REQ_DATAW = REQ_ADDRW + 1 + `DWORD_SIZE + (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH; - localparam RSP_DATAW = `NUM_THREADS + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH; - - // - // handle requests - // - - for (genvar i = 0; i < `NUM_THREADS; ++i) begin - - wire cache_req_ready_in; - wire smem_req_ready_in; - - // select shared memory bus - wire is_smem_addr = core_req_if.valid[i] && `SM_ENABLE - && (core_req_if.addr[i][REQ_ADDRW-1:SMEM_ASHIFT-REQ_ASHIFT] >= (32-SMEM_ASHIFT)'((`SHARED_MEM_BASE_ADDR - `SMEM_SIZE) >> SMEM_ASHIFT)) - && (core_req_if.addr[i][REQ_ADDRW-1:SMEM_ASHIFT-REQ_ASHIFT] < (32-SMEM_ASHIFT)'(`SHARED_MEM_BASE_ADDR >> SMEM_ASHIFT)); - - VX_skid_buffer #( - .DATAW (REQ_DATAW) - ) cache_out_buffer ( - .clk (clk), - .reset (reset), - .valid_in (core_req_if.valid[i] && !is_smem_addr), - .data_in ({core_req_if.addr[i], core_req_if.rw[i], core_req_if.byteen[i], core_req_if.data[i], core_req_if.tag[i]}), - .ready_in (cache_req_ready_in), - .valid_out (cache_req_if.valid[i]), - .data_out ({cache_req_if.addr[i], cache_req_if.rw[i], cache_req_if.byteen[i], cache_req_if.data[i], cache_req_if.tag[i]}), - .ready_out (cache_req_if.ready[i]) - ); - - VX_skid_buffer #( - .DATAW (REQ_DATAW) - ) smem_out_buffer ( - .clk (clk), - .reset (reset), - .valid_in (core_req_if.valid[i] && is_smem_addr), - .data_in ({core_req_if.addr[i], core_req_if.rw[i], core_req_if.byteen[i], core_req_if.data[i], core_req_if.tag[i]}), - .ready_in (smem_req_ready_in), - .valid_out (smem_req_if.valid[i]), - .data_out ({smem_req_if.addr[i], smem_req_if.rw[i], smem_req_if.byteen[i], smem_req_if.data[i], smem_req_if.tag[i]}), - .ready_out (smem_req_if.ready[i]) - ); - - assign core_req_if.ready[i] = is_smem_addr ? smem_req_ready_in : cache_req_ready_in; - end - - // - // handle responses - // - - if (`SM_ENABLE ) begin - - wire [1:0][RSP_DATAW-1:0] rsp_data_in; - wire [1:0] rsp_valid_in; - wire [1:0] rsp_ready_in; - - wire core_rsp_valid; - wire [`NUM_THREADS-1:0] core_rsp_valid_tmask; - - assign rsp_data_in[0] = {cache_rsp_if.valid, cache_rsp_if.data, cache_rsp_if.tag}; - assign rsp_data_in[1] = {smem_rsp_if.valid, smem_rsp_if.data, smem_rsp_if.tag}; - - assign rsp_valid_in[0] = (| cache_rsp_if.valid); - assign rsp_valid_in[1] = (| smem_rsp_if.valid) & `SM_ENABLE; - - VX_stream_arbiter #( - .NUM_REQS (2), - .DATAW (RSP_DATAW), - .BUFFERED (0) - ) rsp_arb ( - .clk (clk), - .reset (reset), - .valid_in (rsp_valid_in), - .data_in (rsp_data_in), - .ready_in (rsp_ready_in), - .valid_out (core_rsp_valid), - .data_out ({core_rsp_valid_tmask, core_rsp_if.data, core_rsp_if.tag}), - .ready_out (core_rsp_if.ready) - ); - - assign cache_rsp_if.ready = rsp_ready_in[0]; - assign smem_rsp_if.ready = rsp_ready_in[1]; - - assign core_rsp_if.valid = {`NUM_THREADS{core_rsp_valid}} & core_rsp_valid_tmask; - - end else begin - - assign core_rsp_if.valid = cache_rsp_if.valid; - assign core_rsp_if.tag = cache_rsp_if.tag; - assign core_rsp_if.data = cache_rsp_if.data; - assign cache_rsp_if.ready = core_rsp_if.ready; - - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_dcache_arb.v b/hw/rtl/VX_dcache_arb.v deleted file mode 100644 index 958146a2..00000000 --- a/hw/rtl/VX_dcache_arb.v +++ /dev/null @@ -1,118 +0,0 @@ -`include "VX_define.vh" - -module VX_mem_arb #( - parameter NUM_REQS = 1, - parameter DATA_WIDTH = 1, - parameter TAG_IN_WIDTH = 1, - parameter TAG_OUT_WIDTH = 1, - parameter BUFFERED_REQ = 0, - parameter BUFFERED_RSP = 0, - - parameter DATA_SIZE = (DATA_WIDTH / 8), - parameter ADDR_WIDTH = 32 - `CLOG2(DATA_SIZE), - parameter LOG_NUM_REQS = `CLOG2(NUM_REQS) -) ( - input wire clk, - input wire reset, - - // input requests - input wire [NUM_REQS-1:0] req_valid_in, - input wire [NUM_REQS-1:0][TAG_IN_WIDTH-1:0] req_tag_in, - input wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] req_addr_in, - input wire [NUM_REQS-1:0] req_rw_in, - input wire [NUM_REQS-1:0][DATA_SIZE-1:0] req_byteen_in, - input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] req_data_in, - output wire [NUM_REQS-1:0] req_ready_in, - - // output request - output wire req_valid_out, - output wire [TAG_OUT_WIDTH-1:0] req_tag_out, - output wire [ADDR_WIDTH-1:0] req_addr_out, - output wire req_rw_out, - output wire [DATA_SIZE-1:0] req_byteen_out, - output wire [DATA_WIDTH-1:0] req_data_out, - input wire req_ready_out, - - // input response - input wire rsp_valid_in, - input wire [TAG_OUT_WIDTH-1:0] rsp_tag_in, - input wire [DATA_WIDTH-1:0] rsp_data_in, - output wire rsp_ready_in, - - // output responses - output wire [NUM_REQS-1:0] rsp_valid_out, - output wire [NUM_REQS-1:0][TAG_IN_WIDTH-1:0] rsp_tag_out, - output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] rsp_data_out, - input wire [NUM_REQS-1:0] rsp_ready_out -); - localparam REQ_DATAW = TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH; - localparam RSP_DATAW = TAG_IN_WIDTH + DATA_WIDTH; - - if (NUM_REQS > 1) begin - - wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_merged_data_in; - for (genvar i = 0; i < NUM_REQS; i++) begin - assign req_merged_data_in[i] = {{req_tag_in[i], LOG_NUM_REQS'(i)}, req_addr_in[i], req_rw_in[i], req_byteen_in[i], req_data_in[i]}; - end - - VX_stream_arbiter #( - .NUM_REQS (NUM_REQS), - .DATAW (REQ_DATAW), - .BUFFERED (BUFFERED_REQ) - ) req_arb ( - .clk (clk), - .reset (reset), - .valid_in (req_valid_in), - .data_in (req_merged_data_in), - .ready_in (req_ready_in), - .valid_out (req_valid_out), - .data_out ({req_tag_out, req_addr_out, req_rw_out, req_byteen_out, req_data_out}), - .ready_out (req_ready_out) - ); - - /////////////////////////////////////////////////////////////////////// - - wire [LOG_NUM_REQS-1:0] rsp_sel = rsp_tag_in [LOG_NUM_REQS-1:0]; - - wire [NUM_REQS-1:0][RSP_DATAW-1:0] rsp_merged_data_out; - for (genvar i = 0; i < NUM_REQS; i++) begin - assign {rsp_tag_out[i], rsp_data_out[i]} = rsp_merged_data_out[i]; - end - - VX_stream_demux #( - .NUM_REQS (NUM_REQS), - .DATAW (RSP_DATAW), - .BUFFERED (BUFFERED_RSP) - ) rsp_demux ( - .clk (clk), - .reset (reset), - .sel (rsp_sel), - .valid_in (rsp_valid_in), - .data_in ({rsp_tag_in[LOG_NUM_REQS +: TAG_IN_WIDTH], rsp_data_in}), - .ready_in (rsp_ready_in), - .valid_out (rsp_valid_out), - .data_out (rsp_merged_data_out), - .ready_out (rsp_ready_out) - ); - - end else begin - - `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - - assign req_valid_out = req_valid_in; - assign req_tag_out = req_tag_in; - assign req_addr_out = req_addr_in; - assign req_rw_out = req_rw_in; - assign req_byteen_out = req_byteen_in; - assign req_data_out = req_data_in; - assign req_ready_in = req_ready_out; - - assign rsp_valid_out = rsp_valid_in; - assign rsp_tag_out = rsp_tag_in; - assign rsp_data_out = rsp_data_in; - assign rsp_ready_in = rsp_ready_out; - - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_tex_cache_arb.v b/hw/rtl/VX_tex_cache_arb.v deleted file mode 100644 index 4aa06b56..00000000 --- a/hw/rtl/VX_tex_cache_arb.v +++ /dev/null @@ -1,136 +0,0 @@ -`include "VX_define.vh" - -module VX_dcache_arb #( - parameter NUM_REQS = 1, - parameter LANES = 1, - parameter WORD_SIZE = 1, - parameter TAG_IN_WIDTH = 1, - parameter TAG_OUT_WIDTH = 1 - parameter LOG_NUM_REQS = `CLOG2(NUM_REQS) -) ( - input wire clk, - input wire reset, - - // input requests - input wire [NUM_REQS-1:0][LANES-1:0] req_valid_in, - input wire [NUM_REQS-1:0][LANES-1:0] req_rw_in, - input wire [NUM_REQS-1:0][LANES-1:0][WORD_SIZE-1:0] req_byteen_in, - input wire [NUM_REQS-1:0][LANES-1:0][`WORD_ADDR_WIDTH-1:0] req_addr_in, - input wire [NUM_REQS-1:0][LANES-1:0][`WORD_WIDTH-1:0] req_data_in, - input wire [NUM_REQS-1:0][LANES-1:0][TAG_IN_WIDTH-1:0] req_tag_in, - output wire [NUM_REQS-1:0][LANES-1:0] req_ready_in, - - // output request - output wire [LANES-1:0] req_valid_out, - output wire [LANES-1:0] req_rw_out, - output wire [LANES-1:0][WORD_SIZE-1:0] req_byteen_out, - output wire [LANES-1:0][`WORD_ADDR_WIDTH-1:0] req_addr_out, - output wire [LANES-1:0][`WORD_WIDTH-1:0] req_data_out, - output wire [LANES-1:0][TAG_OUT_WIDTH-1:0] req_tag_out, - input wire [LANES-1:0] req_ready_out, - - // input response - input wire [LANES-1:0] rsp_valid_in, - input wire [LANES-1:0][`WORD_WIDTH-1:0] rsp_data_in, - input wire [TAG_OUT_WIDTH-1:0] rsp_tag_in, - output wire rsp_ready_in, - - // output responses - output wire [NUM_REQS-1:0][LANES-1:0] rsp_valid_out, - output wire [NUM_REQS-1:0][LANES-1:0][`WORD_WIDTH-1:0] rsp_data_out, - output wire [NUM_REQS-1:0][TAG_IN_WIDTH-1:0] rsp_tag_out, - input wire [NUM_REQS-1:0] rsp_ready_out -); - localparam REQ_DATAW = LANES * (1 + TAG_IN_WIDTH + `WORD_ADDR_WIDTH + 1 + WORD_SIZE + `WORD_WIDTH); - localparam RSP_DATAW = LANES * `WORD_WIDTH + TAG_IN_WIDTH; - - if (NUM_REQS > 1) begin - - wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_merged_data_in; - wire [NUM_REQS-1:0] req_valid_in_any; - - for (genvar i = 0; i < NUM_REQS; i++) begin - assign req_merged_data_in[i] = {req_valid_in[i], req_tag_in[i], req_addr_in[i], req_rw_in[i], req_byteen_in[i], req_data_in[i]}; - assign req_valid_in_any[i] = (| req_valid_in[i]); - end - - wire sel_valid; - wire [LOG_NUM_REQS-1:0] sel_idx; - wire [NUM_REQS-1:0] sel_1hot; - - wire sel_enable = (| req_ready_out); - - VX_rr_arbiter #( - .NUM_REQS(NUM_REQS), - .LOCK_ENABLE(1) - ) sel_arb ( - .clk (clk), - .reset (reset), - .requests (req_valid_in_any), - .enable (sel_enable), - .grant_valid (sel_valid), - .grant_index (sel_idx), - .grant_onehot (sel_1hot) - ); - - wire [LANES-1:0] req_valid_out_unqual; - wire [LANES-1:0][TAG_IN_WIDTH-1:0] req_tag_out_unqual; - - assign {req_valid_out_unqual, req_tag_out_unqual, req_addr_out, req_rw_out, req_byteen_out, req_data_out} = req_merged_data_in[sel_idx]; - - assign req_valid_out = req_valid_out_unqual & {LANES{sel_valid}}; - - for (genvar i = 0; i < LANES; i++) begin - assign req_tag_out[i] = {req_tag_out_unqual[i], sel_idx}; - end - - for (genvar i = 0; i < NUM_REQS; i++) begin - assign req_ready_in[i] = req_ready_out & {LANES{sel_1hot[i]}}; - end - - /////////////////////////////////////////////////////////////////////// - - wire [LOG_NUM_REQS-1:0] rsp_sel = rsp_tag_in [LOG_NUM_REQS-1:0]; - - wire [NUM_REQS-1:0][RSP_DATAW-1:0] rsp_merged_data_out; - for (genvar i = 0; i < NUM_REQS; i++) begin - assign {rsp_tag_out[i], rsp_data_out[i]} = rsp_merged_data_out[i]; - end - - VX_stream_demux #( - .NUM_REQS (NUM_REQS), - .DATAW (RSP_DATAW), - .BUFFERED (BUFFERED_RSP) - ) rsp_demux ( - .clk (clk), - .reset (reset), - .sel (rsp_sel), - .valid_in (rsp_valid_in), - .data_in ({rsp_tag_in[LOG_NUM_REQS +: TAG_IN_WIDTH], rsp_data_in}), - .ready_in (rsp_ready_in), - .valid_out (rsp_valid_out), - .data_out (rsp_merged_data_out), - .ready_out (rsp_ready_out) - ); - - end else begin - - `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - - assign req_valid_out = req_valid_in; - assign req_tag_out = req_tag_in; - assign req_addr_out = req_addr_in; - assign req_rw_out = req_rw_in; - assign req_byteen_out = req_byteen_in; - assign req_data_out = req_data_in; - assign req_ready_in = req_ready_out; - - assign rsp_valid_out = rsp_valid_in; - assign rsp_tag_out = rsp_tag_in; - assign rsp_data_out = rsp_data_in; - assign rsp_ready_in = rsp_ready_out; - - end - -endmodule \ No newline at end of file