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rtl refactoring

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This commit is contained in:
Blaise Tine
2020-05-05 10:46:48 -04:00
parent f142afac80
commit b7e892ee16
39 changed files with 393 additions and 425 deletions
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8
hw/rtl/VX_writeback.v
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@@ -22,9 +22,9 @@ module VX_writeback (
VX_wb_if writeback_tmp_if();
wire exec_wb = (inst_exec_wb_if.wb != 0) && (|inst_exec_wb_if.valid);
wire mem_wb = (mem_wb_if.wb != 0) && (|mem_wb_if.valid);
wire csr_wb = (csr_wb_if.wb != 0) && (|csr_wb_if.valid);
wire exec_wb = (inst_exec_wb_if.wb != 0) && (| inst_exec_wb_if.valid);
wire mem_wb = (mem_wb_if.wb != 0) && (| mem_wb_if.valid);
wire csr_wb = (csr_wb_if.wb != 0) && (| csr_wb_if.valid);
assign no_slot_mem = mem_wb && (exec_wb || csr_wb);
assign no_slot_csr = csr_wb && (exec_wb);
@@ -78,7 +78,7 @@ module VX_writeback (
reg [31:0] last_data_wb /* verilator public */;
always @(posedge clk) begin
if ((|writeback_if.valid) && (writeback_if.wb != 0) && (writeback_if.rd == 28)) begin
if ( (| writeback_if.valid) && (writeback_if.wb != 0) && (writeback_if.rd == 28)) begin
last_data_wb <= use_wb_data[0];
end
end