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rtl refactoring

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This commit is contained in:
Blaise Tine
2020-05-05 10:46:48 -04:00
parent f142afac80
commit b7e892ee16
39 changed files with 393 additions and 425 deletions
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160
hw/rtl/VX_decode.v
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@@ -8,18 +8,15 @@ module VX_decode(
// Outputs
VX_frE_to_bckE_req_if frE_to_bckE_req_if,
VX_wstall_if wstall_if,
VX_join_if join_if,
output wire terminate_sim
VX_join_if join_if
);
wire[31:0] in_instruction = fd_inst_meta_de.instruction;
wire[31:0] in_curr_PC = fd_inst_meta_de.inst_pc;
wire[`NW_BITS-1:0] in_warp_num = fd_inst_meta_de.warp_num;
wire[31:0] in_instruction = fd_inst_meta_de.instruction;
wire[31:0] in_curr_PC = fd_inst_meta_de.inst_pc;
wire[`NW_BITS-1:0] in_warp_num = fd_inst_meta_de.warp_num;
assign frE_to_bckE_req_if.curr_PC = in_curr_PC;
assign frE_to_bckE_req_if.curr_PC = in_curr_PC;
wire[`NUM_THREADS-1:0] in_valid = fd_inst_meta_de.valid;
wire[`NUM_THREADS-1:0] in_valid = fd_inst_meta_de.valid;
wire[6:0] curr_opcode;
@@ -34,7 +31,7 @@ module VX_decode(
wire is_auipc;
wire is_csr;
wire is_csr_immed;
wire is_e_inst;
wire is_etype;
wire is_gpgpu;
wire is_wspawn;
@@ -47,7 +44,6 @@ module VX_decode(
wire[6:0] func7;
wire[11:0] u_12;
wire[7:0] jal_b_19_to_12;
wire jal_b_11;
wire[9:0] jal_b_10_to_1;
@@ -77,11 +73,11 @@ module VX_decode(
reg[4:0] alu_op;
reg[4:0] mul_alu;
reg[19:0] temp_upper_immed;
reg temp_jal;
reg[31:0] temp_jal_offset;
reg[31:0] temp_itype_immed;
reg[2:0] temp_branch_type;
reg temp_branch_stall;
reg temp_jal;
reg[31:0] temp_jal_offset;
reg[31:0] temp_itype_immed;
reg[2:0] temp_branch_type;
reg temp_branch_stall;
assign frE_to_bckE_req_if.valid = fd_inst_meta_de.valid;
@@ -89,12 +85,12 @@ module VX_decode(
assign curr_opcode = in_instruction[6:0];
assign frE_to_bckE_req_if.rd = in_instruction[11:7];
assign frE_to_bckE_req_if.rs1 = in_instruction[19:15];
assign frE_to_bckE_req_if.rs2 = in_instruction[24:20];
assign func3 = in_instruction[14:12];
assign func7 = in_instruction[31:25];
assign u_12 = in_instruction[31:20];
assign frE_to_bckE_req_if.rd = in_instruction[11:7];
assign frE_to_bckE_req_if.rs1 = in_instruction[19:15];
assign frE_to_bckE_req_if.rs2 = in_instruction[24:20];
assign func3 = in_instruction[14:12];
assign func7 = in_instruction[31:25];
assign u_12 = in_instruction[31:20];
assign frE_to_bckE_req_if.PC_next = in_curr_PC + 32'h4;
@@ -110,8 +106,6 @@ module VX_decode(
assign is_auipc = (curr_opcode == `AUIPC_INST);
assign is_csr = (curr_opcode == `SYS_INST) && (func3 != 0);
assign is_csr_immed = (is_csr) && (func3[2] == 1);
// assign is_e_inst = (curr_opcode == `SYS_INST) && (func3 == 0);
assign is_e_inst = in_instruction == 32'h00000073;
assign is_gpgpu = (curr_opcode == `GPGPU_INST);
@@ -132,10 +126,10 @@ module VX_decode(
assign frE_to_bckE_req_if.csr_immed = is_csr_immed;
assign frE_to_bckE_req_if.is_csr = is_csr;
assign frE_to_bckE_req_if.wb = (is_jal || is_jalr || is_e_inst) ? `WB_JAL :
is_linst ? `WB_MEM :
(is_itype || is_rtype || is_lui || is_auipc || is_csr) ? `WB_ALU :
`NO_WB;
assign frE_to_bckE_req_if.wb = (is_jal || is_jalr || is_etype) ? `WB_JAL :
is_linst ? `WB_MEM :
(is_itype || is_rtype || is_lui || is_auipc || is_csr) ? `WB_ALU :
`NO_WB;
assign frE_to_bckE_req_if.rs2_src = (is_itype || is_stype) ? `RS2_IMMED : `RS2_REG;
@@ -145,7 +139,7 @@ module VX_decode(
// UPPER IMMEDIATE
always @(*) begin
case(curr_opcode)
case (curr_opcode)
`LUI_INST: temp_upper_immed = {func7, frE_to_bckE_req_if.rs2, frE_to_bckE_req_if.rs1, func3};
`AUIPC_INST: temp_upper_immed = {func7, frE_to_bckE_req_if.rs2, frE_to_bckE_req_if.rs1, func3};
default: temp_upper_immed = 20'h0;
@@ -165,34 +159,34 @@ module VX_decode(
assign jalr_immed = {func7, frE_to_bckE_req_if.rs2};
assign jal_2_offset = {{20{jalr_immed[11]}}, jalr_immed};
assign jal_sys_cond1 = func3 == 3'h0;
assign jal_sys_cond2 = u_12 < 12'h2;
assign jal_sys_cond1 = (func3 == 3'h0);
assign jal_sys_cond2 = (u_12 < 12'h2);
assign jal_sys_jal = (jal_sys_cond1 && jal_sys_cond2) ? 1'b1 : 1'b0;
assign jal_sys_off = (jal_sys_cond1 && jal_sys_cond2) ? 32'hb0000000 : 32'hdeadbeef;
// JAL
always @(*) begin
case(curr_opcode)
case (curr_opcode)
`JAL_INST:
begin
temp_jal = 1'b1 && (|in_valid);
temp_jal = 1'b1 && (| in_valid);
temp_jal_offset = jal_1_offset;
end
`JALR_INST:
begin
temp_jal = 1'b1 && (|in_valid);
temp_jal = 1'b1 && (| in_valid);
temp_jal_offset = jal_2_offset;
end
`SYS_INST:
begin
// $display("SYS EBREAK %h", (jal_sys_jal && (|in_valid)) );
temp_jal = jal_sys_jal && (|in_valid);
// $display("SYS EBREAK %h", (jal_sys_jal && (| in_valid)));
temp_jal = jal_sys_jal && (| in_valid);
temp_jal_offset = jal_sys_off;
end
default:
begin
temp_jal = 1'b0 && (|in_valid);
temp_jal = 1'b0 && (| in_valid);
temp_jal_offset = 32'hdeadbeef;
end
endcase
@@ -202,12 +196,9 @@ module VX_decode(
assign frE_to_bckE_req_if.jal = temp_jal;
assign frE_to_bckE_req_if.jal_offset = temp_jal_offset;
// wire is_ebreak;
// assign is_ebreak = is_e_inst;
wire ebreak = (curr_opcode == `SYS_INST) && (jal_sys_jal && (|in_valid));
assign frE_to_bckE_req_if.ebreak = ebreak;
assign terminate_sim = is_e_inst;
// ecall/ebreak
assign is_etype = (curr_opcode == `SYS_INST) && jal_sys_jal;
assign frE_to_bckE_req_if.is_etype = is_etype;
// CSR
@@ -222,60 +213,55 @@ module VX_decode(
assign alu_tempp = alu_shift_i ? alu_shift_i_immed : u_12;
always @(*) begin
case(curr_opcode)
`ALU_INST: temp_itype_immed = {{20{alu_tempp[11]}}, alu_tempp};
`S_INST: temp_itype_immed = {{20{func7[6]}}, func7, frE_to_bckE_req_if.rd};
`L_INST: temp_itype_immed = {{20{u_12[11]}}, u_12};
`B_INST: temp_itype_immed = {{20{in_instruction[31]}}, in_instruction[31], in_instruction[7], in_instruction[30:25], in_instruction[11:8]};
default: temp_itype_immed = 32'hdeadbeef;
endcase
case (curr_opcode)
`ALU_INST: temp_itype_immed = {{20{alu_tempp[11]}}, alu_tempp};
`S_INST: temp_itype_immed = {{20{func7[6]}}, func7, frE_to_bckE_req_if.rd};
`L_INST: temp_itype_immed = {{20{u_12[11]}}, u_12};
`B_INST: temp_itype_immed = {{20{in_instruction[31]}}, in_instruction[31], in_instruction[7], in_instruction[30:25], in_instruction[11:8]};
default: temp_itype_immed = 32'hdeadbeef;
endcase
end
assign frE_to_bckE_req_if.itype_immed = temp_itype_immed;
always @(*) begin
case(curr_opcode)
`B_INST:
begin
// $display("BRANCH IN DECODE");
temp_branch_stall = 1'b1 && (|in_valid);
case(func3)
3'h0: temp_branch_type = `BEQ;
3'h1: temp_branch_type = `BNE;
3'h4: temp_branch_type = `BLT;
3'h5: temp_branch_type = `BGT;
3'h6: temp_branch_type = `BLTU;
3'h7: temp_branch_type = `BGTU;
default: temp_branch_type = `NO_BRANCH;
endcase
end
`JAL_INST:
begin
temp_branch_type = `NO_BRANCH;
temp_branch_stall = 1'b1 && (|in_valid);
end
`JALR_INST:
begin
temp_branch_type = `NO_BRANCH;
temp_branch_stall = 1'b1 && (|in_valid);
end
default:
begin
temp_branch_type = `NO_BRANCH;
temp_branch_stall = 1'b0 && (|in_valid);
end
case (curr_opcode)
`B_INST: begin
// $display("BRANCH IN DECODE");
temp_branch_stall = 1'b1 && (| in_valid);
case (func3)
3'h0: temp_branch_type = `BEQ;
3'h1: temp_branch_type = `BNE;
3'h4: temp_branch_type = `BLT;
3'h5: temp_branch_type = `BGT;
3'h6: temp_branch_type = `BLTU;
3'h7: temp_branch_type = `BGTU;
default: temp_branch_type = `NO_BRANCH;
endcase
end
`JAL_INST: begin
temp_branch_type = `NO_BRANCH;
temp_branch_stall = 1'b1 && (| in_valid);
end
`JALR_INST: begin
temp_branch_type = `NO_BRANCH;
temp_branch_stall = 1'b1 && (| in_valid);
end
default: begin
temp_branch_type = `NO_BRANCH;
temp_branch_stall = 1'b0 && (| in_valid);
end
endcase
end
assign frE_to_bckE_req_if.branch_type = temp_branch_type;
assign wstall_if.wstall = (temp_branch_stall || is_tmc || is_split || is_barrier) && (|in_valid);
assign wstall_if.warp_num = in_warp_num;
assign wstall_if.wstall = (temp_branch_stall || is_tmc || is_split || is_barrier) && (| in_valid);
assign wstall_if.warp_num = in_warp_num;
always @(*) begin
// ALU OP
case(func3)
case (func3)
3'h0: alu_op = (curr_opcode == `ALU_INST) ? `ADD : (func7 == 7'h0 ? `ADD : `SUB);
3'h1: alu_op = `SLLA;
3'h2: alu_op = `SLT;
@@ -290,7 +276,7 @@ module VX_decode(
always @(*) begin
// ALU OP
case(func3)
case (func3)
3'h0: mul_alu = `MUL;
3'h1: mul_alu = `MULH;
3'h2: mul_alu = `MULHSU;
@@ -306,7 +292,7 @@ module VX_decode(
assign csr_type = func3[1:0];
always @(*) begin
case(csr_type)
case (csr_type)
2'h1: csr_alu = `CSR_ALU_RW;
2'h2: csr_alu = `CSR_ALU_RS;
2'h3: csr_alu = `CSR_ALU_RC;
@@ -326,7 +312,7 @@ module VX_decode(
assign frE_to_bckE_req_if.alu_op = ((func7[0] == 1'b1) && is_rtype) ? mul_alu : temp_final_alu;
/*always_comb begin
if (1'($time & 1) && |fd_inst_meta_de.valid) begin
if (1'($time & 1) && (| fd_inst_meta_de.valid)) begin
$display("*** %t: decode: opcode=%h", $time, curr_opcode);
end
end*/