diff --git a/hw/Makefile b/hw/Makefile index 7f7d0ef4..7f7f2098 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -25,7 +25,7 @@ THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu .PHONY: build_config build_config: - ./scripts/gen_config.py --outv ./rtl/VX_user_config.vh --outc ./simulate/VX_config.h + ./scripts/gen_config.py --outv ./rtl/VX_user_config.v --outc ./simulate/VX_config.h gen-singlecore: build_config verilator $(VF) -DNDEBUG -cc $(SINGLE_CORE) -CFLAGS '$(CF) -DNDEBUG' diff --git a/hw/modelsim/Makefile b/hw/modelsim/Makefile index 16cec83a..8818b74a 100644 --- a/hw/modelsim/Makefile +++ b/hw/modelsim/Makefile @@ -6,9 +6,9 @@ ALL:sim SRC = \ vortex_dpi.cpp \ vortex_tb.v \ -../rtl/VX_user_config.vh \ -../rtl/VX_config.vh \ -../rtl/VX_define.vh \ +../rtl/VX_user_config.v \ +../rtl/VX_config.v \ +../rtl/VX_define.v \ ../rtl/interfaces/VX_branch_response_inter.v \ ../rtl/interfaces/VX_csr_req_inter.v \ ../rtl/interfaces/VX_csr_wb_inter.v \ diff --git a/hw/modelsim/vortex_tb.v b/hw/modelsim/vortex_tb.v index 4521244a..e9aa5f80 100644 --- a/hw/modelsim/vortex_tb.v +++ b/hw/modelsim/vortex_tb.v @@ -1,4 +1,4 @@ -`include "../VX_define.vh" +`include "../VX_define.v" //`define NUM_BANKS 8 //`define NUM_WORDS_PER_BLOCK 4 diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt index 267a752c..68e363dc 100644 --- a/hw/opae/sources.txt +++ b/hw/opae/sources.txt @@ -9,9 +9,9 @@ vortex_afu.json +incdir+../rtl/cache +incdir+../rtl/libs -../rtl/VX_user_config.vh -../rtl/VX_config.vh -../rtl/VX_define.vh +../rtl/VX_user_config.v +../rtl/VX_config.v +../rtl/VX_define.v ../rtl/cache/VX_cache_config.vh ../rtl/Vortex_Socket.v ../rtl/Vortex_Cluster.v diff --git a/hw/rtl/.gitignore b/hw/rtl/.gitignore index a98a6b43..3d9da51d 100644 --- a/hw/rtl/.gitignore +++ b/hw/rtl/.gitignore @@ -1 +1 @@ -/VX_user_config.vh \ No newline at end of file +/VX_user_config.v \ No newline at end of file diff --git a/hw/rtl/VX_alu.v b/hw/rtl/VX_alu.v index 805856fe..9bacee2d 100644 --- a/hw/rtl/VX_alu.v +++ b/hw/rtl/VX_alu.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_alu ( input wire clk, diff --git a/hw/rtl/VX_back_end.v b/hw/rtl/VX_back_end.v index af0be2fc..ba160d38 100644 --- a/hw/rtl/VX_back_end.v +++ b/hw/rtl/VX_back_end.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_back_end #( parameter CORE_ID = 0 diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.v similarity index 99% rename from hw/rtl/VX_config.vh rename to hw/rtl/VX_config.v index 7d4318d5..042777f0 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.v @@ -1,7 +1,7 @@ `ifndef VX_CONFIG `define VX_CONFIG -`include "VX_user_config.vh" +`include "VX_user_config.v" `ifndef NUM_CLUSTERS `define NUM_CLUSTERS 1 diff --git a/hw/rtl/VX_csr_data.v b/hw/rtl/VX_csr_data.v index 0cd29da0..ac8dfa12 100644 --- a/hw/rtl/VX_csr_data.v +++ b/hw/rtl/VX_csr_data.v @@ -1,4 +1,4 @@ -`include "../VX_define.vh" +`include "../VX_define.v" module VX_csr_data ( input wire clk, // Clock diff --git a/hw/rtl/VX_csr_pipe.v b/hw/rtl/VX_csr_pipe.v index ae711d34..20aec858 100644 --- a/hw/rtl/VX_csr_pipe.v +++ b/hw/rtl/VX_csr_pipe.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_csr_pipe #( parameter CORE_ID = 0 diff --git a/hw/rtl/VX_csr_wrapper.v b/hw/rtl/VX_csr_wrapper.v index f0d97118..b6d879e0 100644 --- a/hw/rtl/VX_csr_wrapper.v +++ b/hw/rtl/VX_csr_wrapper.v @@ -1,5 +1,5 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_csr_wrapper ( VX_csr_req_if csr_req_if, diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index 457ab175..c3f0d580 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -1,5 +1,5 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_decode( // Fetch Inputs diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.v similarity index 95% rename from hw/rtl/VX_define.vh rename to hw/rtl/VX_define.v index e0614dfc..60f56a43 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.v @@ -1,7 +1,7 @@ `ifndef VX_DEFINE `define VX_DEFINE -`include "./VX_config.vh" +`include "./VX_config.v" // `define QUEUE_FORCE_MLAB 1 diff --git a/hw/rtl/VX_dmem_controller.v b/hw/rtl/VX_dmem_controller.v index 83db3804..e415df2a 100644 --- a/hw/rtl/VX_dmem_controller.v +++ b/hw/rtl/VX_dmem_controller.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_dmem_controller ( input wire clk, diff --git a/hw/rtl/VX_execute_unit.v b/hw/rtl/VX_execute_unit.v index 762a3b6d..a3e2d613 100644 --- a/hw/rtl/VX_execute_unit.v +++ b/hw/rtl/VX_execute_unit.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_execute_unit ( input wire clk, diff --git a/hw/rtl/VX_fetch.v b/hw/rtl/VX_fetch.v index db149337..71483684 100644 --- a/hw/rtl/VX_fetch.v +++ b/hw/rtl/VX_fetch.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_fetch ( input wire clk, diff --git a/hw/rtl/VX_front_end.v b/hw/rtl/VX_front_end.v index d5fe06e1..a3a15f55 100644 --- a/hw/rtl/VX_front_end.v +++ b/hw/rtl/VX_front_end.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_front_end ( input wire clk, diff --git a/hw/rtl/VX_gpgpu_inst.v b/hw/rtl/VX_gpgpu_inst.v index 045464d7..0638f81b 100644 --- a/hw/rtl/VX_gpgpu_inst.v +++ b/hw/rtl/VX_gpgpu_inst.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_gpgpu_inst ( // Input diff --git a/hw/rtl/VX_gpr.v b/hw/rtl/VX_gpr.v index c8921fcc..a6829d48 100644 --- a/hw/rtl/VX_gpr.v +++ b/hw/rtl/VX_gpr.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_gpr ( input wire clk, diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index 33fea7fc..32e15d53 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_gpr_stage ( input wire clk, diff --git a/hw/rtl/VX_gpr_wrapper.v b/hw/rtl/VX_gpr_wrapper.v index e5ceea56..b87e34f0 100644 --- a/hw/rtl/VX_gpr_wrapper.v +++ b/hw/rtl/VX_gpr_wrapper.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_gpr_wrapper ( input wire clk, diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index 0e06907b..1ccd506f 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_icache_stage ( input wire clk, diff --git a/hw/rtl/VX_inst_multiplex.v b/hw/rtl/VX_inst_multiplex.v index 19cf7a07..7681dd7f 100644 --- a/hw/rtl/VX_inst_multiplex.v +++ b/hw/rtl/VX_inst_multiplex.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_inst_multiplex ( // Inputs diff --git a/hw/rtl/VX_lsu.v b/hw/rtl/VX_lsu.v index 0425b700..3b63604b 100644 --- a/hw/rtl/VX_lsu.v +++ b/hw/rtl/VX_lsu.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_lsu ( input wire clk, diff --git a/hw/rtl/VX_lsu_addr_gen.v b/hw/rtl/VX_lsu_addr_gen.v index 04d3d8df..be66841a 100644 --- a/hw/rtl/VX_lsu_addr_gen.v +++ b/hw/rtl/VX_lsu_addr_gen.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_lsu_addr_gen ( input wire[`NUM_THREADS-1:0][31:0] base_address, diff --git a/hw/rtl/VX_scheduler.v b/hw/rtl/VX_scheduler.v index 6e89838f..4e5224c7 100644 --- a/hw/rtl/VX_scheduler.v +++ b/hw/rtl/VX_scheduler.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_scheduler ( input wire clk, diff --git a/hw/rtl/VX_warp.v b/hw/rtl/VX_warp.v index f04c4a8d..67a190f1 100644 --- a/hw/rtl/VX_warp.v +++ b/hw/rtl/VX_warp.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_warp ( diff --git a/hw/rtl/VX_warp_scheduler.v b/hw/rtl/VX_warp_scheduler.v index 50aabf86..610ddf73 100644 --- a/hw/rtl/VX_warp_scheduler.v +++ b/hw/rtl/VX_warp_scheduler.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_warp_scheduler ( input wire clk, // Clock diff --git a/hw/rtl/VX_writeback.v b/hw/rtl/VX_writeback.v index f678d39b..5ecc7e2b 100644 --- a/hw/rtl/VX_writeback.v +++ b/hw/rtl/VX_writeback.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_writeback ( input wire clk, diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index 9d3f6a7a..330d01b3 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" `include "VX_cache_config.vh" module Vortex #( diff --git a/hw/rtl/Vortex_Cluster.v b/hw/rtl/Vortex_Cluster.v index d5c38cdd..17a4e33e 100644 --- a/hw/rtl/Vortex_Cluster.v +++ b/hw/rtl/Vortex_Cluster.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" `include "VX_cache_config.vh" module Vortex_Cluster #( diff --git a/hw/rtl/Vortex_Socket.v b/hw/rtl/Vortex_Socket.v index 1b1bf902..1f4ade23 100644 --- a/hw/rtl/Vortex_Socket.v +++ b/hw/rtl/Vortex_Socket.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" `include "VX_cache_config.vh" module Vortex_Socket ( diff --git a/hw/rtl/byte_enabled_simple_dual_port_ram.v b/hw/rtl/byte_enabled_simple_dual_port_ram.v index 657501d8..836b0ca7 100644 --- a/hw/rtl/byte_enabled_simple_dual_port_ram.v +++ b/hw/rtl/byte_enabled_simple_dual_port_ram.v @@ -1,5 +1,5 @@ -`include "VX_define.vh" +`include "VX_define.v" module byte_enabled_simple_dual_port_ram ( diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 2047ac7c..d8547361 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -1,5 +1,5 @@ `include "VX_cache_config.vh" -`include "VX_define.vh" +`include "VX_define.v" module VX_bank #( // Size of cache in bytes parameter CACHE_SIZE_BYTES = 1024, diff --git a/hw/rtl/cache/VX_cache_config.vh b/hw/rtl/cache/VX_cache_config.vh index fa0cf39e..e9edc3f7 100644 --- a/hw/rtl/cache/VX_cache_config.vh +++ b/hw/rtl/cache/VX_cache_config.vh @@ -1,7 +1,7 @@ `ifndef VX_CACHE_CONFIG `define VX_CACHE_CONFIG -`include "../VX_define.vh" +`include "../VX_define.v" // data tid rd wb warp_num read write `define MRVQ_METADATA_SIZE (`WORD_SIZE + `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS) + 3 + 3) diff --git a/hw/rtl/interfaces/VX_branch_response_if.v b/hw/rtl/interfaces/VX_branch_response_if.v index 4a1617cd..dcea6402 100644 --- a/hw/rtl/interfaces/VX_branch_response_if.v +++ b/hw/rtl/interfaces/VX_branch_response_if.v @@ -1,7 +1,7 @@ `ifndef VX_BRANCH_RSP `define VX_BRANCH_RSP -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_branch_response_if (); diff --git a/hw/rtl/interfaces/VX_csr_req_if.v b/hw/rtl/interfaces/VX_csr_req_if.v index 162c8937..d3288d49 100644 --- a/hw/rtl/interfaces/VX_csr_req_if.v +++ b/hw/rtl/interfaces/VX_csr_req_if.v @@ -1,7 +1,7 @@ `ifndef VX_CSR_REQ `define VX_CSR_REQ -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_csr_req_if (); diff --git a/hw/rtl/interfaces/VX_csr_wb_if.v b/hw/rtl/interfaces/VX_csr_wb_if.v index 45df13d0..6e3d2b81 100644 --- a/hw/rtl/interfaces/VX_csr_wb_if.v +++ b/hw/rtl/interfaces/VX_csr_wb_if.v @@ -1,7 +1,7 @@ `ifndef VX_CSR_WB_REQ `define VX_CSR_WB_REQ -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_csr_wb_if (); diff --git a/hw/rtl/interfaces/VX_dcache_request_if.v b/hw/rtl/interfaces/VX_dcache_request_if.v index e61ac455..61717115 100644 --- a/hw/rtl/interfaces/VX_dcache_request_if.v +++ b/hw/rtl/interfaces/VX_dcache_request_if.v @@ -1,7 +1,7 @@ `ifndef VX_DCACHE_REQ `define VX_DCACHE_REQ -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_dcache_request_if (); diff --git a/hw/rtl/interfaces/VX_dcache_response_if.v b/hw/rtl/interfaces/VX_dcache_response_if.v index 280631bb..0ce16b52 100644 --- a/hw/rtl/interfaces/VX_dcache_response_if.v +++ b/hw/rtl/interfaces/VX_dcache_response_if.v @@ -1,7 +1,7 @@ `ifndef VX_DCACHE_RSP `define VX_DCACHE_RSP -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_dcache_response_if (); diff --git a/hw/rtl/interfaces/VX_dram_req_rsp_if.v b/hw/rtl/interfaces/VX_dram_req_rsp_if.v index 08c803d5..5481c7bf 100644 --- a/hw/rtl/interfaces/VX_dram_req_rsp_if.v +++ b/hw/rtl/interfaces/VX_dram_req_rsp_if.v @@ -2,7 +2,7 @@ `ifndef VX_DRAM_REQ_RSP_INTER `define VX_DRAM_REQ_RSP_INTER -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_dram_req_rsp_if #( parameter NUM_BANKS = 8, diff --git a/hw/rtl/interfaces/VX_exec_unit_req_if.v b/hw/rtl/interfaces/VX_exec_unit_req_if.v index f588e41c..ef51eeb8 100644 --- a/hw/rtl/interfaces/VX_exec_unit_req_if.v +++ b/hw/rtl/interfaces/VX_exec_unit_req_if.v @@ -1,7 +1,7 @@ `ifndef VX_EXE_UNIT_REQ_INTER `define VX_EXE_UNIT_REQ_INTER -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_exec_unit_req_if (); diff --git a/hw/rtl/interfaces/VX_frE_to_bckE_req_if.v b/hw/rtl/interfaces/VX_frE_to_bckE_req_if.v index db58eac6..f40d4be6 100644 --- a/hw/rtl/interfaces/VX_frE_to_bckE_req_if.v +++ b/hw/rtl/interfaces/VX_frE_to_bckE_req_if.v @@ -1,7 +1,7 @@ `ifndef VX_FrE_to_BE_INTER `define VX_FrE_to_BE_INTER -`include "VX_define.vh" +`include "VX_define.v" interface VX_frE_to_bckE_req_if (); diff --git a/hw/rtl/interfaces/VX_gpr_data_if.v b/hw/rtl/interfaces/VX_gpr_data_if.v index 622f54a5..67f7d364 100644 --- a/hw/rtl/interfaces/VX_gpr_data_if.v +++ b/hw/rtl/interfaces/VX_gpr_data_if.v @@ -2,7 +2,7 @@ `ifndef VX_gpr_data_INTER `define VX_gpr_data_INTER -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_gpr_data_if (); diff --git a/hw/rtl/interfaces/VX_gpr_jal_if.v b/hw/rtl/interfaces/VX_gpr_jal_if.v index 17f68359..01282523 100644 --- a/hw/rtl/interfaces/VX_gpr_jal_if.v +++ b/hw/rtl/interfaces/VX_gpr_jal_if.v @@ -1,7 +1,7 @@ `ifndef VX_GPR_JAL_INTER `define VX_GPR_JAL_INTER -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_gpr_jal_if (); diff --git a/hw/rtl/interfaces/VX_gpr_read_if.v b/hw/rtl/interfaces/VX_gpr_read_if.v index c5796c45..22b0f41c 100644 --- a/hw/rtl/interfaces/VX_gpr_read_if.v +++ b/hw/rtl/interfaces/VX_gpr_read_if.v @@ -1,7 +1,7 @@ `ifndef VX_GPR_READ `define VX_GPR_READ -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_gpr_read_if (); diff --git a/hw/rtl/interfaces/VX_gpu_inst_req_if.v b/hw/rtl/interfaces/VX_gpu_inst_req_if.v index a394b12d..eccdf494 100644 --- a/hw/rtl/interfaces/VX_gpu_inst_req_if.v +++ b/hw/rtl/interfaces/VX_gpu_inst_req_if.v @@ -1,7 +1,7 @@ `ifndef VX_GPU_INST_REQ_IN `define VX_GPU_INST_REQ_IN -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_gpu_inst_req_if(); diff --git a/hw/rtl/interfaces/VX_icache_request_if.v b/hw/rtl/interfaces/VX_icache_request_if.v index 6d02f106..1377133f 100644 --- a/hw/rtl/interfaces/VX_icache_request_if.v +++ b/hw/rtl/interfaces/VX_icache_request_if.v @@ -2,7 +2,7 @@ `ifndef VX_ICACHE_REQ `define VX_ICACHE_REQ -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_icache_request_if (); diff --git a/hw/rtl/interfaces/VX_icache_response_if.v b/hw/rtl/interfaces/VX_icache_response_if.v index d73775e4..9e471943 100644 --- a/hw/rtl/interfaces/VX_icache_response_if.v +++ b/hw/rtl/interfaces/VX_icache_response_if.v @@ -1,7 +1,7 @@ `ifndef VX_ICACHE_RSP `define VX_ICACHE_RSP -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_icache_response_if (); diff --git a/hw/rtl/interfaces/VX_inst_exec_wb_if.v b/hw/rtl/interfaces/VX_inst_exec_wb_if.v index 47581879..62721891 100644 --- a/hw/rtl/interfaces/VX_inst_exec_wb_if.v +++ b/hw/rtl/interfaces/VX_inst_exec_wb_if.v @@ -2,7 +2,7 @@ `ifndef VX_EXEC_UNIT_WB_INST_INTER `define VX_EXEC_UNIT_WB_INST_INTER -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_inst_exec_wb_if (); diff --git a/hw/rtl/interfaces/VX_inst_mem_wb_if.v b/hw/rtl/interfaces/VX_inst_mem_wb_if.v index ed30b3cf..8b62a1e3 100644 --- a/hw/rtl/interfaces/VX_inst_mem_wb_if.v +++ b/hw/rtl/interfaces/VX_inst_mem_wb_if.v @@ -2,7 +2,7 @@ `ifndef VX_MEM_WB_INST_INTER `define VX_MEM_WB_INST_INTER -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_inst_mem_wb_if (); diff --git a/hw/rtl/interfaces/VX_inst_meta_if.v b/hw/rtl/interfaces/VX_inst_meta_if.v index f925a3be..15b65ef7 100644 --- a/hw/rtl/interfaces/VX_inst_meta_if.v +++ b/hw/rtl/interfaces/VX_inst_meta_if.v @@ -1,7 +1,7 @@ `ifndef VX_F_D_INTER `define VX_F_D_INTER -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_inst_meta_if (); diff --git a/hw/rtl/interfaces/VX_jal_response_if.v b/hw/rtl/interfaces/VX_jal_response_if.v index fde25f7a..da2813dc 100644 --- a/hw/rtl/interfaces/VX_jal_response_if.v +++ b/hw/rtl/interfaces/VX_jal_response_if.v @@ -2,7 +2,7 @@ `ifndef VX_JAL_RSP `define VX_JAL_RSP -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_jal_response_if (); diff --git a/hw/rtl/interfaces/VX_join_if.v b/hw/rtl/interfaces/VX_join_if.v index fa712bd1..14a69a2b 100644 --- a/hw/rtl/interfaces/VX_join_if.v +++ b/hw/rtl/interfaces/VX_join_if.v @@ -2,7 +2,7 @@ `ifndef VX_JOIN_INTER `define VX_JOIN_INTER -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_join_if (); diff --git a/hw/rtl/interfaces/VX_lsu_req_if.v b/hw/rtl/interfaces/VX_lsu_req_if.v index 9db222ad..24597910 100644 --- a/hw/rtl/interfaces/VX_lsu_req_if.v +++ b/hw/rtl/interfaces/VX_lsu_req_if.v @@ -2,7 +2,7 @@ `ifndef VX_LSU_REQ_INTER `define VX_LSU_REQ_INTER -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_lsu_req_if (); diff --git a/hw/rtl/interfaces/VX_mem_req_if.v b/hw/rtl/interfaces/VX_mem_req_if.v index 5c6afa4b..f0a68f3b 100644 --- a/hw/rtl/interfaces/VX_mem_req_if.v +++ b/hw/rtl/interfaces/VX_mem_req_if.v @@ -1,7 +1,7 @@ `ifndef VX_MEM_REQ_IN `define VX_MEM_REQ_IN -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_mem_req_if (); diff --git a/hw/rtl/interfaces/VX_mw_wb_if.v b/hw/rtl/interfaces/VX_mw_wb_if.v index a0d3f5ea..adba1ae9 100644 --- a/hw/rtl/interfaces/VX_mw_wb_if.v +++ b/hw/rtl/interfaces/VX_mw_wb_if.v @@ -2,7 +2,7 @@ `ifndef VX_MW_WB_INTER `define VX_MW_WB_INTER -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_mw_wb_if (); diff --git a/hw/rtl/interfaces/VX_warp_ctl_if.v b/hw/rtl/interfaces/VX_warp_ctl_if.v index 254e0a90..7002d85c 100644 --- a/hw/rtl/interfaces/VX_warp_ctl_if.v +++ b/hw/rtl/interfaces/VX_warp_ctl_if.v @@ -2,7 +2,7 @@ `ifndef VX_WARP_CTL_INTER `define VX_WARP_CTL_INTER -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_warp_ctl_if (); diff --git a/hw/rtl/interfaces/VX_wb_if.v b/hw/rtl/interfaces/VX_wb_if.v index a87ee192..6b5cf512 100644 --- a/hw/rtl/interfaces/VX_wb_if.v +++ b/hw/rtl/interfaces/VX_wb_if.v @@ -1,7 +1,7 @@ `ifndef VX_WB_INTER `define VX_WB_INTER -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_wb_if (); diff --git a/hw/rtl/interfaces/VX_wstall_if.v b/hw/rtl/interfaces/VX_wstall_if.v index b981cd91..67c32a6d 100644 --- a/hw/rtl/interfaces/VX_wstall_if.v +++ b/hw/rtl/interfaces/VX_wstall_if.v @@ -1,7 +1,7 @@ `ifndef VX_WSTALL_INTER `define VX_WSTALL_INTER -`include "../VX_define.vh" +`include "../VX_define.v" interface VX_wstall_if(); diff --git a/hw/rtl/libs/VX_generic_priority_encoder.v b/hw/rtl/libs/VX_generic_priority_encoder.v index fb852564..481a54e4 100644 --- a/hw/rtl/libs/VX_generic_priority_encoder.v +++ b/hw/rtl/libs/VX_generic_priority_encoder.v @@ -1,7 +1,7 @@ `ifndef VX_GENERIC_PRIORITY_ENCODER `define VX_GENERIC_PRIORITY_ENCODER -`include "VX_define.vh" +`include "VX_define.v" module VX_generic_priority_encoder #( diff --git a/hw/rtl/libs/VX_priority_encoder.v b/hw/rtl/libs/VX_priority_encoder.v index b6e04433..0f559f81 100644 --- a/hw/rtl/libs/VX_priority_encoder.v +++ b/hw/rtl/libs/VX_priority_encoder.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_priority_encoder ( input wire[`NUM_WARPS-1:0] valids, diff --git a/hw/rtl/libs/VX_priority_encoder_w_mask.v b/hw/rtl/libs/VX_priority_encoder_w_mask.v index d6a2405c..e14816bd 100644 --- a/hw/rtl/libs/VX_priority_encoder_w_mask.v +++ b/hw/rtl/libs/VX_priority_encoder_w_mask.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_define.v" module VX_priority_encoder_w_mask #( parameter N = 10 ) ( diff --git a/hw/rtl/pipe_regs/VX_d_e_reg.v b/hw/rtl/pipe_regs/VX_d_e_reg.v index f4e6b2f8..061ea1b4 100644 --- a/hw/rtl/pipe_regs/VX_d_e_reg.v +++ b/hw/rtl/pipe_regs/VX_d_e_reg.v @@ -1,4 +1,4 @@ -`include "../VX_define.vh" +`include "../VX_define.v" module VX_d_e_reg ( input wire clk, diff --git a/hw/rtl/pipe_regs/VX_f_d_reg.v b/hw/rtl/pipe_regs/VX_f_d_reg.v index 1b8d8170..abe3a495 100644 --- a/hw/rtl/pipe_regs/VX_f_d_reg.v +++ b/hw/rtl/pipe_regs/VX_f_d_reg.v @@ -1,4 +1,4 @@ -`include "../VX_define.vh" +`include "../VX_define.v" module VX_f_d_reg ( input wire clk, @@ -24,5 +24,4 @@ module VX_f_d_reg ( .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.inst_pc, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) ); - endmodule \ No newline at end of file diff --git a/hw/rtl/pipe_regs/VX_i_d_reg.v b/hw/rtl/pipe_regs/VX_i_d_reg.v index e0cfb2b6..43a90196 100644 --- a/hw/rtl/pipe_regs/VX_i_d_reg.v +++ b/hw/rtl/pipe_regs/VX_i_d_reg.v @@ -1,4 +1,4 @@ -`include "../VX_define.vh" +`include "../VX_define.v" module VX_i_d_reg ( input wire clk, @@ -25,5 +25,4 @@ module VX_i_d_reg ( .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.inst_pc, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) ); - endmodule \ No newline at end of file diff --git a/hw/scripts/gen_config.py b/hw/scripts/gen_config.py index 426c83a8..ab96cc52 100755 --- a/hw/scripts/gen_config.py +++ b/hw/scripts/gen_config.py @@ -61,7 +61,7 @@ translation_rules = [ (re.compile(r'^( *)`ifndef ([^ ]+)$'), r'\1#ifndef \2'), (re.compile(r'^( *)`define ([^ ]+)$'), r'\1#define \2'), # (re.compile(r'^( *)`include "\./VX_define_synth\.v"$'), r'\1#include "VX_define_synth.h"'), - (re.compile(r'^( *)`include "VX_user_config\.vh"$'), r''), + (re.compile(r'^( *)`include "VX_user_config\.v"$'), r''), (re.compile(r'^( *)`define ([^ ]+) (.+)$'), r'\1#define \2 \3'), (re.compile(r'^( *)`endif$'), r'\1#endif'), (re.compile(r'^( *)// (.*)$'), r'\1// \2'), @@ -93,9 +93,9 @@ if args.outc != 'none': // auto-generated by gen_config.py. DO NOT EDIT // Generated at {date} -// Translated from VX_config.vh: +// Translated from VX_config.v: '''[1:].format(date=datetime.now()), file=f) - with open(path.join(script_dir, '../rtl/VX_config.vh'), 'r') as r: + with open(path.join(script_dir, '../rtl/VX_config.v'), 'r') as r: for line in r: if in_expansion: f.write(post_process_line(line)) diff --git a/hw/syn/synopsys/esyn.tcl b/hw/syn/synopsys/esyn.tcl index 9268b364..85d82049 100644 --- a/hw/syn/synopsys/esyn.tcl +++ b/hw/syn/synopsys/esyn.tcl @@ -4,9 +4,9 @@ set link_library [concat ./NanGate_15nm_OCL.db] set symbol_library {} set target_library [concat ./NanGate_15nm_OCL.db] -set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_config.vh VX_user_config.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v \ +set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_config.v VX_user_config.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v \ ] -# set verilog_files [ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \ +# set verilog_files [ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \ # ] set top_level Vortex diff --git a/hw/syn/synopsys/fsyn.tcl b/hw/syn/synopsys/fsyn.tcl index b6c30524..e1d9902d 100644 --- a/hw/syn/synopsys/fsyn.tcl +++ b/hw/syn/synopsys/fsyn.tcl @@ -2,9 +2,9 @@ set search_path [concat ../../models/memory/cln28hpm/rf2_128x128_wm1 ../../mod set link_library [concat NanGate_15nm_OCL.db] set symbol_library {} set target_library [concat NanGate_15nm_OCL.db] -set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_bank_valid.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v rf2_128x128_wm1.v \ +set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_bank_valid.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v rf2_128x128_wm1.v \ ] -# set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v \ +# set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v \ # ] set top_level Vortex diff --git a/hw/syn/synopsys/syn.tcl b/hw/syn/synopsys/syn.tcl index 951adaa8..2f9c1a65 100755 --- a/hw/syn/synopsys/syn.tcl +++ b/hw/syn/synopsys/syn.tcl @@ -3,9 +3,9 @@ set link_library [concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_ set symbol_library {} set target_library [concat sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db] -set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v \ +set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v \ ] -# set verilog_files [ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \ +# set verilog_files [ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \ # ] set top_level Vortex