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Merge branch 'master' of https://github.gatech.edu/casl/Vortex

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This commit is contained in:
fares
2019-11-25 02:52:22 -05:00
parent 44b8cdf5c1 a38987e7af
commit b752ce5485
76 changed files with 386716 additions and 14 deletions
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8
simX/enc.cpp
View File

@@ -285,8 +285,8 @@ Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx, trace_in
inst.setVlsWidth((code>>shift_func3) & func3_mask);
inst.setSrcReg((code>>shift_rs2) & reg_mask);
inst.setVmask((code>>shift_vmask));
inst.setVmop((code>>shift_vmop) && func3_mask);
inst.setVnf((code>>shift_vnf) && func3_mask);
inst.setVmop((code>>shift_vmop) & func3_mask);
inst.setVnf((code>>shift_vnf) & func3_mask);
trace_inst->valid_inst = true;
trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
@@ -300,8 +300,8 @@ Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx, trace_in
inst.setVlsWidth((code>>shift_func3) & func3_mask);
inst.setSrcReg((code>>shift_rs2) & reg_mask);
inst.setVmask((code>>shift_vmask));
inst.setVmop((code>>shift_vmop) && func3_mask);
inst.setVnf((code>>shift_vnf) && func3_mask);
inst.setVmop((code>>shift_vmop) & func3_mask);
inst.setVnf((code>>shift_vnf) & func3_mask);
trace_inst->valid_inst = true;
trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);

181
simX/instruction.cpp
View File

@@ -2016,6 +2016,64 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
}
}
break;
case 37: //vmul
{
D(3, "vmul");
uint8_t *result_ptr;
vector<Reg<char *>> & vr1 = c.vreg[rsrc[0]];
vector<Reg<char *>> & vr2 = c.vreg[rsrc[1]];
vector<Reg<char *>> & vd = c.vreg[rdest];
if(c.vtype.vsew == 8){
for(uint8_t i = 0; i < c.vl; i++){
uint8_t *first_ptr = (uint8_t *)vr1[i].val;
uint8_t *second_ptr = (uint8_t *)vr2[i].val;
uint8_t result = (*first_ptr * *second_ptr);
D(3,"Comparing " << *first_ptr << " + " << *second_ptr << " = " << result);
result_ptr = (uint8_t *) vd[i].val;
*result_ptr = result;
}
for(uint8_t i = c.vl; i < VLMAX; i++){
result_ptr = (uint8_t *) vd[i].val;
*result_ptr = 0;
}
}
else if(c.vtype.vsew == 16) {
uint16_t *result_ptr;
for(uint16_t i = 0; i < c.vl; i++){
uint16_t *first_ptr = (uint16_t *)vr1[i].val;
uint16_t *second_ptr = (uint16_t *)vr2[i].val;
uint16_t result = (*first_ptr * *second_ptr);
D(3,"Comparing " << *first_ptr << " + " << *second_ptr << " = " << result);
result_ptr = (uint16_t *) vd[i].val;
*result_ptr = result;
}
for(uint16_t i = c.vl; i < VLMAX; i++){
result_ptr = (uint16_t *) vd[i].val;
*result_ptr = 0;
}
} else if(c.vtype.vsew == 32) {
uint32_t *result_ptr;
for(uint32_t i = 0; i < c.vl; i++){
uint32_t *first_ptr = (uint32_t *)vr1[i].val;
uint32_t *second_ptr = (uint32_t *)vr2[i].val;
uint32_t result = (*first_ptr * *second_ptr);
D(3,"Comparing " << *first_ptr << " + " << *second_ptr << " = " << result);
result_ptr = (uint32_t *) vd[i].val;
*result_ptr = result;
}
for(Word i = c.vl; i < VLMAX; i++){
result_ptr = (uint32_t *) vd[i].val;
*result_ptr = 0;
}
}
}
break;
case 45: //vmacc
{
D(3, "vmacc");
@@ -2077,6 +2135,129 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
}
}
break;
case 6:
{
switch(func6)
{
case 0:
{
D(3, "vmadd.vx");
uint8_t *result_ptr;
//vector<Reg<char *>> & vr1 = c.vreg[rsrc[0]];
vector<Reg<char *>> & vr2 = c.vreg[rsrc[1]];
vector<Reg<char *>> & vd = c.vreg[rdest];
if(c.vtype.vsew == 8){
for(uint8_t i = 0; i < c.vl; i++){
//uint8_t *first_ptr = (uint8_t *)vr1[i].val;
uint8_t *second_ptr = (uint8_t *)vr2[i].val;
uint8_t result = (reg[rsrc[0]] + *second_ptr);
D(3,"Comparing " << reg[rsrc[0]] << " + " << *second_ptr << " = " << result);
result_ptr = (uint8_t *) vd[i].val;
*result_ptr = result;
}
for(uint8_t i = c.vl; i < VLMAX; i++){
result_ptr = (uint8_t *) vd[i].val;
*result_ptr = 0;
}
}
else if(c.vtype.vsew == 16) {
uint16_t *result_ptr;
for(uint16_t i = 0; i < c.vl; i++){
//uint16_t *first_ptr = (uint16_t *)vr1[i].val;
uint16_t *second_ptr = (uint16_t *)vr2[i].val;
uint16_t result = (reg[rsrc[0]] + *second_ptr);
D(3,"Comparing " << reg[rsrc[0]] << " + " << *second_ptr << " = " << result);
result_ptr = (uint16_t *) vd[i].val;
*result_ptr = result;
}
for(uint16_t i = c.vl; i < VLMAX; i++){
result_ptr = (uint16_t *) vd[i].val;
*result_ptr = 0;
}
} else if(c.vtype.vsew == 32) {
uint32_t *result_ptr;
for(uint32_t i = 0; i < c.vl; i++){
//uint32_t *first_ptr = (uint32_t *)vr1[i].val;
uint32_t *second_ptr = (uint32_t *)vr2[i].val;
uint32_t result = (reg[rsrc[0]] + *second_ptr);
D(3,"Comparing " << reg[rsrc[0]] << " + " << *second_ptr << " = " << result);
result_ptr = (uint32_t *) vd[i].val;
*result_ptr = result;
}
for(Word i = c.vl; i < VLMAX; i++){
result_ptr = (uint32_t *) vd[i].val;
*result_ptr = 0;
}
}
}
break;
case 37: //vmul.vx
{
D(3, "vmul.vx");
uint8_t *result_ptr;
//vector<Reg<char *>> & vr1 = c.vreg[rsrc[0]];
vector<Reg<char *>> & vr2 = c.vreg[rsrc[1]];
vector<Reg<char *>> & vd = c.vreg[rdest];
if(c.vtype.vsew == 8){
for(uint8_t i = 0; i < c.vl; i++){
//uint8_t *first_ptr = (uint8_t *)vr1[i].val;
uint8_t *second_ptr = (uint8_t *)vr2[i].val;
uint8_t result = (reg[rsrc[0]] * *second_ptr);
D(3,"Comparing " << reg[rsrc[0]] << " + " << *second_ptr << " = " << result);
result_ptr = (uint8_t *) vd[i].val;
*result_ptr = result;
}
for(uint8_t i = c.vl; i < VLMAX; i++){
result_ptr = (uint8_t *) vd[i].val;
*result_ptr = 0;
}
}
else if(c.vtype.vsew == 16) {
uint16_t *result_ptr;
for(uint16_t i = 0; i < c.vl; i++){
//uint16_t *first_ptr = (uint16_t *)vr1[i].val;
uint16_t *second_ptr = (uint16_t *)vr2[i].val;
uint16_t result = (reg[rsrc[0]] * *second_ptr);
D(3,"Comparing " << reg[rsrc[0]] << " + " << *second_ptr << " = " << result);
result_ptr = (uint16_t *) vd[i].val;
*result_ptr = result;
}
for(uint16_t i = c.vl; i < VLMAX; i++){
result_ptr = (uint16_t *) vd[i].val;
*result_ptr = 0;
}
} else if(c.vtype.vsew == 32) {
uint32_t *result_ptr;
for(uint32_t i = 0; i < c.vl; i++){
//uint32_t *first_ptr = (uint32_t *)vr1[i].val;
uint32_t *second_ptr = (uint32_t *)vr2[i].val;
uint32_t result = (reg[rsrc[0]] * *second_ptr);
D(3,"Comparing " << reg[rsrc[0]] << " + " << *second_ptr << " = " << result);
result_ptr = (uint32_t *) vd[i].val;
*result_ptr = result;
}
for(Word i = c.vl; i < VLMAX; i++){
result_ptr = (uint32_t *) vd[i].val;
*result_ptr = 0;
}
}
}
break;
}
}
break;
case 7:
{
is_vec = true;

2
simX/out Normal file
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@@ -0,0 +1,2 @@
verilator --compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS '-std=c++11 -fPIC -O3' -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1
Makefile:26: recipe for target 'simX' failed

5
simX/test_benchmark.sh
View File

@@ -1,6 +1,7 @@
echo start > results.txt
# echo ../kernel/vortex_test.hex
make
printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../rvvector/benchmark_temp/vx_vec_benchmark.hex -s -b 1> emulator.debug
#cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../benchmarks/vector/vecadd/vx_vec_vecadd.hex -s -b 1> emulator.debug
#cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../benchmarks/vector/saxpy/vx_vec_saxpy.hex -s -b 1> emulator.debug
cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../benchmarks/vector/sgemm_nn/vx_vec_sgemm_nn.hex -s -b 1> emulator.debug

3
simX/test_riscv.sh
View File

@@ -3,4 +3,5 @@ echo start > results.txt
# echo ../kernel/vortex_test.hex
make
printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../runtime/mains/simple/vx_simple_main.hex -s -b 1> emulator.debug
#cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../runtime/mains/simple/vx_simple_main.hex -s -b 1> emulator.debug
cd obj_dir && ./Vcache_simX -E -a rv32i --core /home/priya/Desktop/new_vortex/Vortex/rvvector/benchmark_temp/vx_vec_benchmark.hex -s -b 1> emulator.debug

6
simX/test_vec.sh Executable file
View File

@@ -0,0 +1,6 @@
echo start > results.txt
# echo ../kernel/vortex_test.hex
make
printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../rvvector/basic/vx_vector_main.hex -s -b 1> emulator.debug