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proper srams

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This commit is contained in:
Richard Yan
2024-05-07 13:52:07 -07:00
parent 85213d2876
commit b70df8cbc9
1 changed files with 93 additions and 30 deletions
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123
hw/rtl/libs/VX_dp_ram.sv
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@@ -160,37 +160,69 @@ module VX_dp_ram #(
assign rdata = ram[raddr]; assign rdata = ram[raddr];
end end
end else begin end else begin
if (OUT_REG != 0) begin `ifndef FIRESIM
reg [DATAW-1:0] ram [SIZE-1:0]; if (DATAW == 1024 && SIZE == 16) begin // dcache data
reg [DATAW-1:0] rdata_r; dcache_data ram (
`RAM_INITIALIZATION .R0_addr(raddr),
always @(posedge clk) begin .R0_clk(clk),
if (write) begin .R0_data(rdata),
for (integer i = 0; i < WRENW; ++i) begin .R0_en(read),
if (wren[i]) .W0_addr(waddr),
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; .W0_clk(clk),
end .W0_data(wdata),
end .W0_en(write),
if (read) begin .W0_mask(wren)
rdata_r <= ram[raddr]; );
end end else if (DATAW == 305 && SIZE == 8) begin // mshr
end cache_mshr ram (
assign rdata = rdata_r; .R0_addr(raddr),
.R0_clk(clk),
.R0_data(rdata),
.R0_en(read),
.W0_addr(waddr),
.W0_clk(clk),
.W0_data(wdata),
.W0_en(write)
);
end else if (DATAW == 24 && SIZE == 16) begin // dcache tags
dcache_tags ram (
.R0_addr(raddr),
.R0_clk(clk),
.R0_data(rdata),
.R0_en(read),
.W0_addr(waddr),
.W0_clk(clk),
.W0_data(wdata),
.W0_en(write)
);
end else if (DATAW == 1024 && SIZE == 128) begin // icache data
icache_data ram (
.R0_addr(raddr),
.R0_clk(clk),
.R0_data(rdata),
.R0_en(read),
.W0_addr(waddr),
.W0_clk(clk),
.W0_data(wdata),
.W0_en(write),
.W0_mask(wren)
);
end else if (DATAW == 21 && SIZE == 128) begin // icache tags
icache_tags ram (
.R0_addr(raddr),
.R0_clk(clk),
.R0_data(rdata),
.R0_en(read),
.W0_addr(waddr),
.W0_clk(clk),
.W0_data(wdata),
.W0_en(write)
);
end else begin end else begin
if (NO_RWCHECK != 0) begin `endif
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0]; if (OUT_REG != 0) begin
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
end
assign rdata = ram[raddr];
end else begin
reg [DATAW-1:0] ram [SIZE-1:0]; reg [DATAW-1:0] ram [SIZE-1:0];
reg [DATAW-1:0] rdata_r;
`RAM_INITIALIZATION `RAM_INITIALIZATION
always @(posedge clk) begin always @(posedge clk) begin
if (write) begin if (write) begin
@@ -199,10 +231,41 @@ module VX_dp_ram #(
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end end
end end
if (read) begin
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end else begin
if (NO_RWCHECK != 0) begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
end
assign rdata = ram[raddr];
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
end
assign rdata = ram[raddr];
end end
assign rdata = ram[raddr];
end end
`ifndef FIRESIM
end end
`endif
end end
`endif `endif
end else begin end else begin