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proper srams

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This commit is contained in:
Richard Yan
2024-05-07 13:52:07 -07:00
parent 85213d2876
commit b70df8cbc9
1 changed files with 93 additions and 30 deletions
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63
hw/rtl/libs/VX_dp_ram.sv
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@@ -160,6 +160,66 @@ module VX_dp_ram #(
assign rdata = ram[raddr]; assign rdata = ram[raddr];
end end
end else begin end else begin
`ifndef FIRESIM
if (DATAW == 1024 && SIZE == 16) begin // dcache data
dcache_data ram (
.R0_addr(raddr),
.R0_clk(clk),
.R0_data(rdata),
.R0_en(read),
.W0_addr(waddr),
.W0_clk(clk),
.W0_data(wdata),
.W0_en(write),
.W0_mask(wren)
);
end else if (DATAW == 305 && SIZE == 8) begin // mshr
cache_mshr ram (
.R0_addr(raddr),
.R0_clk(clk),
.R0_data(rdata),
.R0_en(read),
.W0_addr(waddr),
.W0_clk(clk),
.W0_data(wdata),
.W0_en(write)
);
end else if (DATAW == 24 && SIZE == 16) begin // dcache tags
dcache_tags ram (
.R0_addr(raddr),
.R0_clk(clk),
.R0_data(rdata),
.R0_en(read),
.W0_addr(waddr),
.W0_clk(clk),
.W0_data(wdata),
.W0_en(write)
);
end else if (DATAW == 1024 && SIZE == 128) begin // icache data
icache_data ram (
.R0_addr(raddr),
.R0_clk(clk),
.R0_data(rdata),
.R0_en(read),
.W0_addr(waddr),
.W0_clk(clk),
.W0_data(wdata),
.W0_en(write),
.W0_mask(wren)
);
end else if (DATAW == 21 && SIZE == 128) begin // icache tags
icache_tags ram (
.R0_addr(raddr),
.R0_clk(clk),
.R0_data(rdata),
.R0_en(read),
.W0_addr(waddr),
.W0_clk(clk),
.W0_data(wdata),
.W0_en(write)
);
end else begin
`endif
if (OUT_REG != 0) begin if (OUT_REG != 0) begin
reg [DATAW-1:0] ram [SIZE-1:0]; reg [DATAW-1:0] ram [SIZE-1:0];
reg [DATAW-1:0] rdata_r; reg [DATAW-1:0] rdata_r;
@@ -203,6 +263,9 @@ module VX_dp_ram #(
assign rdata = ram[raddr]; assign rdata = ram[raddr];
end end
end end
`ifndef FIRESIM
end
`endif
end end
`endif `endif
end else begin end else begin