From b6ce2dd3b87b286483fbdc6455dfed22d243b255 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 21 Apr 2020 02:08:20 -0700 Subject: [PATCH] opae build fix --- hw/opae/sources.txt | 21 +++------ hw/rtl/VX_warp.v | 106 +++++++++++++++++++++----------------------- 2 files changed, 57 insertions(+), 70 deletions(-) diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt index 516aa4b2..fc16d66c 100644 --- a/hw/opae/sources.txt +++ b/hw/opae/sources.txt @@ -18,17 +18,13 @@ vortex_afu.json ../rtl/interfaces/VX_branch_rsp_if.v ../rtl/interfaces/VX_inst_meta_if.v ../rtl/interfaces/VX_join_if.v -../rtl/interfaces/VX_icache_response_if.v +../rtl/interfaces/VX_icache_rsp_if.v ../rtl/interfaces/VX_inst_exec_wb_if.v ../rtl/interfaces/VX_gpu_dcache_dram_req_if.v ../rtl/interfaces/VX_csr_req_if.v -../rtl/interfaces/VX_icache_request_if.v ../rtl/interfaces/VX_gpu_dcache_rsp_if.v ../rtl/interfaces/VX_frE_to_bckE_req_if.v -../rtl/interfaces/VX_dram_req_rsp_if.v -../rtl/interfaces/VX_dcache_request_if.v ../rtl/interfaces/VX_gpr_data_if.v -../rtl/interfaces/VX_dcache_response_if.v ../rtl/interfaces/VX_csr_wb_if.v ../rtl/interfaces/VX_gpu_dcache_req_if.v ../rtl/interfaces/VX_lsu_req_if.v @@ -39,8 +35,7 @@ vortex_afu.json ../rtl/interfaces/VX_wstall_if.v ../rtl/interfaces/VX_wb_if.v ../rtl/interfaces/VX_gpr_read_if.v -../rtl/interfaces/VX_mem_req_if.v -../rtl/interfaces/VX_jal_response_if.v +../rtl/interfaces/VX_jal_rsp_if.v ../rtl/interfaces/VX_warp_ctl_if.v ../rtl/interfaces/VX_gpu_dcache_snp_req_if.v ../rtl/interfaces/VX_gpu_dcache_dram_rsp_if.v @@ -54,6 +49,8 @@ vortex_afu.json ../rtl/libs/VX_generic_priority_encoder.v ../rtl/libs/VX_priority_encoder.v ../rtl/libs/VX_generic_queue.v +../rtl/libs/VX_byte_enabled_dual_port_ram.v +../rtl/libs/VX_countones.v ../rtl/Vortex_Socket.v ../rtl/Vortex_Cluster.v @@ -62,19 +59,17 @@ vortex_afu.json ../rtl/VX_back_end.v ../rtl/VX_fetch.v ../rtl/VX_scheduler.v -../rtl/VX_execute_unit.v +../rtl/VX_exec_unit.v ../rtl/VX_warp.v ../rtl/VX_icache_stage.v ../rtl/VX_gpr_wrapper.v -../rtl/byte_enabled_simple_dual_port_ram.v ../rtl/VX_gpgpu_inst.v ../rtl/VX_writeback.v -../rtl/VX_countones.v ../rtl/VX_csr_pipe.v -../rtl/VX_warp_scheduler.v +../rtl/VX_warp_sched.v ../rtl/VX_gpr.v ../rtl/VX_gpr_stage.v -../rtl/VX_dmem_controller.v +../rtl/VX_dmem_ctrl.v ../rtl/VX_alu.v ../rtl/VX_csr_data.v ../rtl/VX_lsu.v @@ -91,8 +86,6 @@ vortex_afu.json ../rtl/cache/VX_cache_dram_req_arb.v ../rtl/cache/VX_cache_dfq_queue.v ../rtl/cache/VX_cache_wb_sel_merge.v -../rtl/cache/VX_mrv_queue.v -../rtl/cache/VX_dcache_llv_resp_bank_sel.v ../rtl/cache/VX_tag_data_access.v ../rtl/cache/VX_cache.v ../rtl/cache/VX_cache_core_req_bank_sel.v diff --git a/hw/rtl/VX_warp.v b/hw/rtl/VX_warp.v index 83ac48c1..c34c984e 100644 --- a/hw/rtl/VX_warp.v +++ b/hw/rtl/VX_warp.v @@ -19,69 +19,63 @@ module VX_warp ( output wire[`NUM_THREADS-1:0] valid ); - reg[31:0] real_PC; - logic [31:0] temp_PC; - logic [31:0] use_PC; - reg[`NUM_THREADS-1:0] valid; + reg [31:0] real_PC; + logic [31:0] temp_PC; + logic [31:0] use_PC; + reg [`NUM_THREADS-1:0] valid_t; + reg [`NUM_THREADS-1:0] valid_zero; - reg[`NUM_THREADS-1:0] valid_zero; - - integer ini_cur_th = 0; - initial begin - real_PC = 0; - for (ini_cur_th = 1; ini_cur_th < `NUM_THREADS; ini_cur_th=ini_cur_th+1) begin - valid[ini_cur_th] = 0; // Thread 1 active - valid_zero[ini_cur_th] = 0; - end - valid[0] = 1; - valid_zero[0] = 0; + integer ini_cur_th = 0; + initial begin + real_PC = 0; + for (ini_cur_th = 1; ini_cur_th < `NUM_THREADS; ini_cur_th=ini_cur_th+1) begin + valid_t[ini_cur_th] = 0; // Thread 1 active + valid_zero[ini_cur_th] = 0; end + valid_t = 1; + valid_zero[0] = 0; + end - - always @(posedge clk) begin - if (remove) begin - valid <= valid_zero; - end else if (change_mask) begin - valid <= thread_mask; - end + always @(posedge clk) begin + if (remove) begin + valid_t <= valid_zero; + end else if (change_mask) begin + valid_t <= thread_mask; end + end - - genvar out_cur_th; - generate - for (out_cur_th = 0; out_cur_th < `NUM_THREADS; out_cur_th = out_cur_th+1) begin : valid_assign - assign valid[out_cur_th] = change_mask ? thread_mask[out_cur_th] : stall ? 1'b0 : valid[out_cur_th]; - end - endgenerate - - - always @(*) begin - if (jal == 1'b1) begin - temp_PC = jal_dest; - // $display("LINKING TO %h", temp_PC); - end else if (branch_dir == 1'b1) begin - temp_PC = branch_dest; - end else begin - temp_PC = real_PC; - end + genvar out_cur_th; + generate + for (out_cur_th = 0; out_cur_th < `NUM_THREADS; out_cur_th = out_cur_th+1) begin : valid_assign + assign valid[out_cur_th] = change_mask ? thread_mask[out_cur_th] : stall ? 1'b0 : valid_t[out_cur_th]; end + endgenerate - assign use_PC = temp_PC; - assign PC = temp_PC; - - always @(posedge clk) begin - if (reset) begin - real_PC <= 0; - end else if (wspawn == 1'b1) begin - // $display("Inside warp ***** Spawn @ %H",wspawn_pc); - real_PC <= wspawn_pc; - end else if (!stall) begin - real_PC <= use_PC + 32'h4; - end else begin - real_PC <= use_PC; - end - + always @(*) begin + if (jal == 1'b1) begin + temp_PC = jal_dest; + // $display("LINKING TO %h", temp_PC); + end else if (branch_dir == 1'b1) begin + temp_PC = branch_dest; + end else begin + temp_PC = real_PC; end - + end + + assign use_PC = temp_PC; + assign PC = temp_PC; + + always @(posedge clk) begin + if (reset) begin + real_PC <= 0; + end else if (wspawn == 1'b1) begin + // $display("Inside warp ***** Spawn @ %H",wspawn_pc); + real_PC <= wspawn_pc; + end else if (!stall) begin + real_PC <= use_PC + 32'h4; + end else begin + real_PC <= use_PC; + end + end endmodule \ No newline at end of file