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rtl refactoring

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This commit is contained in:
Blaise Tine
2020-05-10 09:52:38 -04:00
parent cc84e0691c
commit b6c4aa0baa
4 changed files with 70 additions and 70 deletions
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2
hw/rtl/cache/VX_cache_dram_req_arb.v vendored
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@@ -24,7 +24,7 @@ module VX_cache_dram_req_arb #(
// Writeback Request
input wire [NUM_BANKS-1:0] per_bank_dram_wb_req_valid,
input wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_wb_req_addr,
input wire [NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] per_bank_dram_wb_req_data,
input wire [NUM_BANKS-1:0][`BANK_LINE_WIDTH-1:0] per_bank_dram_wb_req_data,
output wire [NUM_BANKS-1:0] per_bank_dram_wb_queue_pop,
// Merged Request