Use skid buffer on CSR IO bus to stop backpressure delay propagation into csr_unit

hw/rtl/libs/VX_cam_buffer.v

@@ -7,13 +7,16 @@ module VX_cam_buffer #(
 ) (
     input  wire clk,
     input  wire reset,
+
     output wire [ADDRW-1:0] write_addr,
     input  wire [DATAW-1:0] write_data,            
     input  wire acquire_slot,
+
     input  wire [ADDRW-1:0] read_addr,
     output wire [DATAW-1:0] read_data,
     input  wire [ADDRW-1:0] release_addr,
     input  wire release_slot,
+    
     output wire full
 );
     reg [SIZE-1:0] free_slots, free_slots_n;

hw/rtl/libs/VX_countones.v

@@ -5,7 +5,7 @@ module VX_countones #(
     parameter N = 10,
     parameter N_BITS = $clog2(N+1)
 ) (
-    input wire [N-1:0]  valids,
+    input wire [N-1:0]       valids,
     output wire [N_BITS-1:0] count    
 );
     reg [N_BITS-1:0] count_r;

hw/rtl/libs/VX_divide.v

@@ -10,7 +10,7 @@ module VX_divide #(
     parameter LATENCY = 0
 ) (
     input wire clk,
-    input wire enable,
+    input wire enable, 
     input wire [WIDTHN-1:0] numer,
     input wire [WIDTHD-1:0] denom,
     output wire [WIDTHQ-1:0] quotient,

hw/rtl/libs/VX_elastic_buffer.v

@@ -3,28 +3,35 @@
 module VX_elastic_buffer #(
     parameter DATAW    = 1,
     parameter SIZE     = 2,
-    parameter BUFFERED = 0
+    parameter BUFFERED = 0,
+    parameter FASTRAM  = 0
 ) ( 
     input  wire             clk,
     input  wire             reset,
+
     input  wire             valid_in,
     output wire             ready_in,        
     input  wire [DATAW-1:0] data_in,
+    
     output wire [DATAW-1:0] data_out,
     input  wire             ready_out,
     output wire             valid_out
 ); 
     wire empty, full;
 
+    wire push = valid_in && ready_in;
+    wire pop  = valid_out && ready_out;
+
     VX_generic_queue #(
         .DATAW    (DATAW),
         .SIZE     (SIZE),
-        .BUFFERED (BUFFERED)
+        .BUFFERED (BUFFERED),
+        .FASTRAM  (FASTRAM)
     ) queue (
         .clk    (clk),
         .reset  (reset),
-        .push   (valid_in),
-        .pop    (ready_out),
+        .push   (push),
+        .pop    (pop),
         .data_in(data_in),
         .data_out(data_out),        
         .empty  (empty),

hw/rtl/libs/VX_generic_queue.v

@@ -9,7 +9,7 @@ module VX_generic_queue #(
     parameter FASTRAM  = 0
 ) ( 
     input  wire             clk,
-    input  wire             reset,
+    input  wire             reset,    
     input  wire             push,
     input  wire             pop,        
     input  wire [DATAW-1:0] data_in,