fpga_synthesis merge

simX/include/archdef.h

@@ -16,17 +16,21 @@ namespace Harp {
   public:
     struct Undefined {};
 
+<<<<<<< HEAD
     ArchDef(const std::string &s, bool cpu_mode = false) 
       : cpu_mode_(cpu_mode) {
+=======
+    ArchDef(const std::string &s, int num_warps = 32, int num_threads = 32) {
+>>>>>>> fpga_synthesis
       std::istringstream iss(s.c_str());
             
       wordSize = 4;
       encChar = 'w';
       nRegs = 32;
       nPRegs = 0;
-      nThds = 32;
-      nWarps = 32;
-
+      nWarps = num_warps;
+      nThds = num_threads;
+      
       extent = EXT_WARPS;
 
       // if (!iss) { extent = EXT_NULL; return; }

simX/include/core.h

@@ -19,9 +19,9 @@
 #include "Vcache_simX.h"
 #include "verilated.h"
 
-// #ifdef VCD_OUTPUT
+#ifdef VCD_OUTPUT
 #include <verilated_vcd_c.h>
-// #endif
+#endif
 
 
 #include "trace.h"

simX/include/debug.h

@@ -4,20 +4,34 @@
 #ifndef __DEBUG_H
 #define __DEBUG_H
 
-// #define USE_DEBUG 9
-// #define USE_DEBUG 3
+//#define USE_DEBUG 9
 
 #ifdef USE_DEBUG
 #include <iostream>
 
 #define D(lvl, x) do { \
   using namespace std; \
-  if ((lvl) == USE_DEBUG) { \
+  if ((lvl) <= USE_DEBUG) { \
     cout << "DEBUG " << __FILE__ << ':' << dec << __LINE__ << ": " \
          << x << endl; \
   } \
 } while(0)
 
+#define DPH(lvl, x) do { \
+  using namespace std; \
+  if ((lvl) <= USE_DEBUG) { \
+    cout << "DEBUG " << __FILE__ << ':' << dec << __LINE__ << ": " \
+         << x; \
+  } \
+} while(0)
+
+#define DPN(lvl, x) do { \
+  using namespace std; \
+  if ((lvl) <= USE_DEBUG) { \
+    cout << x; \
+  } \
+} while(0)
+
 #define D_RAW(x) do { \
   std::cout << x; \
 } while (0)
@@ -25,6 +39,8 @@
 #else
 
 #define D(lvl, x) do {} while(0)
+#define DPH(lvl, x) do {} while(0)
+#define DPN(lvl, x) do {} while(0)
 #define D_RAW(x) do {} while(0)
 #endif