OPAE rtl fixes
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@@ -13,13 +13,15 @@ module VX_generic_queue #(
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output wire full,
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`IGNORE_WARNINGS_END
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out
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output wire [DATAW-1:0] data_out,
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output wire [`LOG2UP(SIZE+1)-1:0] size
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);
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if (SIZE == 0) begin
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assign empty = 1;
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assign data_out = data_in;
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assign full = 0;
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assign size = 0;
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end else begin // (SIZE > 0)
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@@ -59,6 +61,8 @@ module VX_generic_queue #(
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assign data_out = head_r;
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assign empty = (size_r == 0);
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assign full = (size_r != 0);
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assign size = size_r;
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end else begin // (SIZE > 1)
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reg [DATAW-1:0] curr_r;
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@@ -131,8 +135,9 @@ module VX_generic_queue #(
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end
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assign data_out = bypass_r ? curr_r : head_r;
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assign empty = empty_r;
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assign full = full_r;
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assign empty = empty_r;
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assign full = full_r;
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assign size = size_r;
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end
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end
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