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critical path optimization - fpga fmax @4c = ~212 mhz

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This commit is contained in:
Blaise Tine
2020-12-26 03:28:32 -08:00
parent d5c6b9b4d9
commit b459192dec
11 changed files with 216 additions and 169 deletions
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33
hw/rtl/cache/VX_cache.v vendored
View File

@@ -91,6 +91,11 @@ module VX_cache #(
wire [NUM_BANKS-1:0] per_bank_core_req_valid;
wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid;
wire [NUM_BANKS-1:0] per_bank_core_req_rw;
wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen;
wire [NUM_BANKS-1:0][`WORD_ADDR_WIDTH-1:0] per_bank_core_req_addr;
wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag;
wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data;
wire [NUM_BANKS-1:0] per_bank_core_req_ready;
wire [NUM_BANKS-1:0] per_bank_core_rsp_valid;
@@ -122,7 +127,8 @@ module VX_cache #(
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.NUM_REQS (NUM_REQS)
.NUM_REQS (NUM_REQS),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH)
) cache_core_req_bank_sel (
.clk (clk),
.reset (reset),
@@ -132,11 +138,20 @@ module VX_cache #(
`UNUSED_PIN (bank_stalls),
`endif
.core_req_valid (core_req_valid),
.core_req_rw (core_req_rw),
.core_req_byteen(core_req_byteen),
.core_req_addr (core_req_addr),
.core_req_data (core_req_data),
.core_req_tag (core_req_tag),
.core_req_ready (core_req_ready),
.per_bank_valid (per_bank_core_req_valid),
.per_bank_tid (per_bank_core_req_tid),
.per_bank_ready (per_bank_core_req_ready)
.per_bank_core_req_valid (per_bank_core_req_valid),
.per_bank_core_req_tid (per_bank_core_req_tid),
.per_bank_core_req_rw (per_bank_core_req_rw),
.per_bank_core_req_byteen(per_bank_core_req_byteen),
.per_bank_core_req_addr (per_bank_core_req_addr),
.per_bank_core_req_tag (per_bank_core_req_tag),
.per_bank_core_req_data (per_bank_core_req_data),
.per_bank_core_req_ready (per_bank_core_req_ready)
);
assign dram_req_tag = dram_req_addr;
@@ -179,11 +194,11 @@ module VX_cache #(
// Core Req
assign curr_bank_core_req_valid = per_bank_core_req_valid[i];
assign curr_bank_core_req_tid = per_bank_core_req_tid[i];
assign curr_bank_core_req_addr = core_req_addr[per_bank_core_req_tid[i]];
assign curr_bank_core_req_rw = core_req_rw[per_bank_core_req_tid[i]];
assign curr_bank_core_req_byteen = core_req_byteen[per_bank_core_req_tid[i]];
assign curr_bank_core_req_data = core_req_data[per_bank_core_req_tid[i]];
assign curr_bank_core_req_tag = core_req_tag[per_bank_core_req_tid[i]];
assign curr_bank_core_req_addr = per_bank_core_req_addr[i];
assign curr_bank_core_req_rw = per_bank_core_req_rw[i];
assign curr_bank_core_req_byteen = per_bank_core_req_byteen[i];
assign curr_bank_core_req_data = per_bank_core_req_data[i];
assign curr_bank_core_req_tag = per_bank_core_req_tag[i];
assign per_bank_core_req_ready[i] = curr_bank_core_req_ready;
// Core WB

110
hw/rtl/cache/VX_cache_core_req_bank_sel.v vendored
View File

@@ -8,48 +8,80 @@ module VX_cache_core_req_bank_sel #(
// Number of banks
parameter NUM_BANKS = 1,
// Number of Word requests per cycle
parameter NUM_REQS = 1
parameter NUM_REQS = 1,
// core request tag size
parameter CORE_TAG_WIDTH = 1
) (
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] core_req_valid,
input wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
output wire [NUM_REQS-1:0] core_req_ready,
output wire [NUM_BANKS-1:0] per_bank_valid,
output wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_tid,
input wire [NUM_BANKS-1:0] per_bank_ready,
output wire [63:0] bank_stalls
input wire clk,
input wire reset,
output wire [63:0] bank_stalls,
input wire [NUM_REQS-1:0] core_req_valid,
input wire [NUM_REQS-1:0] core_req_rw,
input wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen,
input wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
input wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_req_data,
input wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
output wire [NUM_REQS-1:0] core_req_ready,
output wire [NUM_BANKS-1:0] per_bank_core_req_valid,
output wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid,
output wire [NUM_BANKS-1:0] per_bank_core_req_rw,
output wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen,
output wire [NUM_BANKS-1:0][`WORD_ADDR_WIDTH-1:0] per_bank_core_req_addr,
output wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag,
output wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data,
input wire [NUM_BANKS-1:0] per_bank_core_req_ready
);
if (NUM_BANKS > 1) begin
reg [NUM_BANKS-1:0] per_bank_valid_r;
reg [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_tid_r;
reg [NUM_REQS-1:0] core_req_ready_r;
reg [NUM_BANKS-1:0] core_req_sel_r;
wire [NUM_REQS-1:0][`BANK_BITS-1:0] core_req_bid;
if (NUM_BANKS > 1) begin
reg [NUM_BANKS-1:0] per_bank_core_req_valid_r;
reg [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid_r;
reg [NUM_BANKS-1:0] per_bank_core_req_rw_r;
reg [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen_r;
reg [NUM_BANKS-1:0][`WORD_ADDR_WIDTH-1:0] per_bank_core_req_addr_r;
reg [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag_r;
reg [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data_r;
reg [NUM_REQS-1:0] core_req_ready_r;
reg [NUM_BANKS-1:0] core_req_sel_r;
wire [NUM_REQS-1:0][`BANK_BITS-1:0] core_req_bid;
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_req_bid[i] = core_req_addr[i][`BANK_SELECT_ADDR_RNG];
end
always @(*) begin
per_bank_valid_r = 0;
per_bank_tid_r = 'x;
per_bank_core_req_valid_r = 0;
per_bank_core_req_tid_r = 'x;
per_bank_core_req_rw_r = 'x;
per_bank_core_req_byteen_r= 'x;
per_bank_core_req_addr_r = 'x;
per_bank_core_req_tag_r = 'x;
per_bank_core_req_data_r = 'x;
for (integer i = NUM_REQS-1; i >= 0; --i) begin
if (core_req_valid[i]) begin
per_bank_valid_r[core_req_bid[i]] = 1;
per_bank_tid_r[core_req_bid[i]] = `REQS_BITS'(i);
per_bank_core_req_valid_r[core_req_bid[i]] = 1;
per_bank_core_req_tid_r[core_req_bid[i]] = `REQS_BITS'(i);
per_bank_core_req_rw_r[core_req_bid[i]] = core_req_rw[i];
per_bank_core_req_byteen_r[core_req_bid[i]]= core_req_byteen[i];
per_bank_core_req_addr_r[core_req_bid[i]] = core_req_addr[i];
per_bank_core_req_tag_r[core_req_bid[i]] = core_req_tag[i];
per_bank_core_req_data_r[core_req_bid[i]] = core_req_data[i];
end
end
end
always @(*) begin
core_req_ready_r = 0;
core_req_sel_r = 0;
core_req_sel_r = 0;
for (integer j = 0; j < NUM_BANKS; ++j) begin
for (integer i = 0; i < NUM_REQS; ++i) begin
if (core_req_valid[i] && (core_req_bid[i] == `BANK_BITS'(j))) begin
core_req_ready_r[i] = per_bank_ready[j];
core_req_sel_r[i] = 1;
core_req_ready_r[i] = per_bank_core_req_ready[j];
core_req_sel_r[i] = 1;
break;
end
end
@@ -65,20 +97,30 @@ module VX_cache_core_req_bank_sel #(
end
end
assign per_bank_valid = per_bank_valid_r;
assign per_bank_tid = per_bank_tid_r;
assign core_req_ready = core_req_ready_r;
assign bank_stalls = bank_stalls_r;
assign bank_stalls = bank_stalls_r;
assign per_bank_core_req_valid = per_bank_core_req_valid_r;
assign per_bank_core_req_tid = per_bank_core_req_tid_r;
assign per_bank_core_req_rw = per_bank_core_req_rw_r;
assign per_bank_core_req_byteen = per_bank_core_req_byteen_r;
assign per_bank_core_req_addr = per_bank_core_req_addr_r;
assign per_bank_core_req_tag = per_bank_core_req_tag_r;
assign per_bank_core_req_data = per_bank_core_req_data_r;
assign core_req_ready = core_req_ready_r;
end else begin
end else begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (core_req_valid)
`UNUSED_VAR (core_req_addr)
assign per_bank_valid = core_req_valid;
assign per_bank_tid = 0;
assign core_req_ready[0] = per_bank_ready;
assign bank_stalls = 0;
assign bank_stalls = 0;
assign per_bank_core_req_valid = core_req_valid;
assign per_bank_core_req_tid[0] = 0;
assign per_bank_core_req_rw[0] = core_req_rw;
assign per_bank_core_req_byteen[0] = core_req_byteen;
assign per_bank_core_req_addr[0] = core_req_addr;
assign per_bank_core_req_tag[0] = core_req_tag;
assign per_bank_core_req_data[0] = core_req_data;
assign core_req_ready[0] = per_bank_core_req_ready;
end
endmodule

8
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
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@@ -37,7 +37,6 @@ module VX_cache_core_rsp_merge #(
if (CORE_TAG_ID_BITS != 0) begin
reg [CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual;
reg [CORE_TAG_ID_BITS-1:0] sel_tag_id;
reg core_rsp_valid_unaual_any;
wire core_rsp_ready_unqual;
@@ -46,21 +45,18 @@ module VX_cache_core_rsp_merge #(
core_rsp_valid_unaual_any = 0;
core_rsp_tag_unqual = 'x;
core_rsp_data_unqual = 'x;
core_rsp_bank_select = 0;
core_rsp_bank_select = 0;
sel_tag_id = 'x;
for (integer i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_rsp_valid[i]) begin
core_rsp_tag_unqual = per_bank_core_rsp_tag[i];
sel_tag_id = per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0];
break;
end
end
for (integer i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_rsp_valid[i]
&& (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == sel_tag_id)) begin
&& (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == core_rsp_tag_unqual[CORE_TAG_ID_BITS-1:0])) begin
core_rsp_valid_unaual_any = 1;
core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] = 1;
core_rsp_data_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i];