From b3e54a837ee5f0dbbfaaa90b002de6b2dcc4337d Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 20 Jul 2021 12:01:04 -0700 Subject: [PATCH] minor update --- hw/rtl/VX_icache_stage.v | 26 +++++++++++++++++++------- hw/rtl/cache/VX_bank.v | 23 ++++++++++++----------- 2 files changed, 31 insertions(+), 18 deletions(-) diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index 74965c56..881528e3 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -22,6 +22,8 @@ module VX_icache_stage #( `UNUSED_PARAM (CORE_ID) `UNUSED_VAR (reset) + localparam OUTPUT_REG = 0; + wire icache_req_fire = icache_req_if.valid && icache_req_if.ready; wire [`NW_BITS-1:0] req_tag = ifetch_req_if.wid; @@ -58,14 +60,24 @@ module VX_icache_stage #( assign icache_req_if.tag = req_tag; `endif - assign ifetch_rsp_if.valid = icache_rsp_if.valid; - assign ifetch_rsp_if.tmask = rsp_tmask; - assign ifetch_rsp_if.wid = rsp_tag; - assign ifetch_rsp_if.PC = rsp_PC; - assign ifetch_rsp_if.data = icache_rsp_if.data; + wire [`NW_BITS-1:0] rsp_wid = rsp_tag; + + wire stall_out = ~ifetch_rsp_if.ready && (0 == OUTPUT_REG && ifetch_rsp_if.valid); + + VX_pipe_register #( + .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + 32), + .RESETW (1), + .DEPTH (OUTPUT_REG) + ) pipe_reg ( + .clk (clk), + .reset (reset), + .enable (!stall_out), + .data_in ({icache_rsp_if.valid, rsp_wid, rsp_tmask, rsp_PC, icache_rsp_if.data}), + .data_out ({ifetch_rsp_if.valid, ifetch_rsp_if.wid, ifetch_rsp_if.tmask, ifetch_rsp_if.PC, ifetch_rsp_if.data}) + ); // Can accept new response? - assign icache_rsp_if.ready = ifetch_rsp_if.ready; + assign icache_rsp_if.ready = ~stall_out; `SCOPE_ASSIGN (icache_req_fire, icache_req_fire); `SCOPE_ASSIGN (icache_req_wid, ifetch_req_if.wid); @@ -80,7 +92,7 @@ module VX_icache_stage #( if (icache_req_if.valid && icache_req_if.ready) begin $display("%t: I$%0d req: wid=%0d, PC=%0h", $time, CORE_ID, ifetch_req_if.wid, ifetch_req_if.PC); end - if (icache_rsp_if.valid && icache_rsp_if.ready) begin + if (ifetch_rsp_if.valid && ifetch_rsp_if.ready) begin $display("%t: I$%0d rsp: wid=%0d, PC=%0h, data=%0h", $time, CORE_ID, ifetch_rsp_if.wid, ifetch_rsp_if.PC, ifetch_rsp_if.data); end end diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index b1874543..cf0a5317 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -113,7 +113,7 @@ module VX_bank #( VX_elastic_buffer #( .DATAW (CORE_TAG_WIDTH + 1 + `LINE_ADDR_WIDTH + (1 + `UP(`WORD_SELECT_BITS) + WORD_SIZE + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS), .SIZE (CREQ_SIZE), - .BUFFERED (1) + .BUFFERED (CREQ_SIZE > 2) ) core_req_queue ( .clk (clk), .reset (reset), @@ -126,10 +126,8 @@ module VX_bank #( ); wire mshr_alm_full; - wire mshr_push; wire mshr_pop; wire mshr_pending; - wire mshr_valid; wire [`LINE_ADDR_WIDTH-1:0] mshr_addr; wire [CORE_TAG_WIDTH-1:0] mshr_tag; @@ -268,6 +266,9 @@ module VX_bank #( end `endif + wire do_lookup_st0 = valid_st0 && ~is_fill_st0; + wire do_fill_st0 = valid_st0 && is_fill_st0 && !crsq_in_stall; + wire tag_match_st0; VX_tag_access #( @@ -288,9 +289,9 @@ module VX_bank #( `endif // read/Fill - .lookup (valid_st0 && !is_fill_st0), + .lookup (do_lookup_st0), .addr (addr_st0), - .fill (valid_st0 && is_fill_st0 && !crsq_in_stall), + .fill (do_fill_st0), .is_flush (is_flush_st0), .tag_match (tag_match_st0) ); @@ -395,14 +396,14 @@ module VX_bank #( .wdata (wdata_st1) ); - assign mshr_push = valid_st1 && mshr_push_st1; + wire mshr_push = valid_st1 && mshr_push_st1; wire mshr_dequeue = valid_st1 && is_mshr_st1 && !mshr_push_st1 && crsq_in_ready; wire mshr_restore = is_mshr_st1; // push a missed request as 'ready' if it was a forced miss that actually had a hit // or the fill request for this block is comming wire mshr_init_ready_state = !miss_st1 || incoming_fill_qual_st1; - + // use memory rsp or core req address to lookup the mshr wire [`LINE_ADDR_WIDTH-1:0] lookup_addr = mem_rsp_valid ? mem_rsp_addr : creq_addr; @@ -461,7 +462,7 @@ module VX_bank #( wire [NUM_PORTS-1:0][`REQS_BITS-1:0] crsq_tid; wire [CORE_TAG_WIDTH-1:0] crsq_tag; - assign crsq_in_valid = valid_st1 && crsq_push_st1; + assign crsq_in_valid = valid_st1 && crsq_push_st1; assign crsq_in_stall = crsq_in_valid && !crsq_in_ready; assign crsq_pmask = pmask_st1; @@ -477,8 +478,8 @@ module VX_bank #( end VX_elastic_buffer #( - .DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS), - .SIZE (CRSQ_SIZE) + .DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS), + .SIZE (CRSQ_SIZE) ) core_rsp_req ( .clk (clk), .reset (reset), @@ -550,7 +551,7 @@ module VX_bank #( always @(posedge clk) begin /*if (crsq_in_fire && (NUM_PORTS > 1) && $countones(crsq_pmask) > 1) begin $display("%t: *** cache%0d:%0d multi-port-out: pmask=%b, addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, crsq_pmask, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), crsq_tag); - end */ + end*/ if (valid_st1 && !is_fill_st1 && miss_st1 && incoming_fill_qual_st1) begin $display("%t: *** cache%0d:%0d miss with incoming fill - addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID)); assert(!is_mshr_st1);