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Fix assignment for perf counters

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This commit is contained in:
Hansung Kim
2024-03-19 14:06:44 -07:00
parent df4b21507e
commit b25deb8a2e
2 changed files with 59 additions and 27 deletions
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82
hw/rtl/core/VX_core.sv
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@@ -334,24 +334,41 @@ module VX_core import VX_gpu_pkg::*; #(
assign pipeline_perf_if.stores = perf_stores; assign pipeline_perf_if.stores = perf_stores;
assign pipeline_perf_if.load_latency = perf_dcache_lat; assign pipeline_perf_if.load_latency = perf_dcache_lat;
assign pipeline_perf_if.ifetch_latency = perf_icache_lat; assign pipeline_perf_if.ifetch_latency = perf_icache_lat;
real instrs = commit_csr_if.instret; int instrs;
real cycles = sched_csr_if.cycles; assign instrs = commit_csr_if.instret;
real icache_lat = perf_icache_lat; int cycles;
real ifetches = perf_ifetches; assign cycles = sched_csr_if.cycles;
real dcache_lat = perf_dcache_lat; int icache_lat;
real loads = perf_loads; assign icache_lat = perf_icache_lat;
real scheduler_idles = pipeline_perf_if.sched_idles; int ifetches;
real scheduler_stalls = pipeline_perf_if.sched_stalls; assign ifetches = perf_ifetches;
real ibuf_stalls = pipeline_perf_if.ibf_stalls; int dcache_lat;
real scrb_alu_per_core = pipeline_perf_if.units_uses[`EX_ALU]; assign dcache_lat = perf_dcache_lat;
real scrb_fpu_per_core = pipeline_perf_if.units_uses[`EX_FPU]; int loads;
real scrb_lsu_per_core = pipeline_perf_if.units_uses[`EX_LSU]; assign loads = perf_loads;
real scrb_sfu_per_core = pipeline_perf_if.units_uses[`EX_SFU]; int scheduler_idles;
real scrb_tot = scrb_alu_per_core+scrb_fpu_per_core+scrb_lsu_per_core+scrb_sfu_per_core; assign scheduler_idles = pipeline_perf_if.sched_idles;
int scheduler_stalls;
assign scheduler_stalls = pipeline_perf_if.sched_stalls;
int ibuf_stalls;
assign ibuf_stalls = pipeline_perf_if.ibf_stalls;
int scrb_alu_per_core;
assign scrb_alu_per_core = pipeline_perf_if.units_uses[`EX_ALU];
int scrb_fpu_per_core;
assign scrb_fpu_per_core = pipeline_perf_if.units_uses[`EX_FPU];
int scrb_lsu_per_core;
assign scrb_lsu_per_core = pipeline_perf_if.units_uses[`EX_LSU];
int scrb_sfu_per_core;
assign scrb_sfu_per_core = pipeline_perf_if.units_uses[`EX_SFU];
int scrb_tot;
assign scrb_tot = scrb_alu_per_core+scrb_fpu_per_core+scrb_lsu_per_core+scrb_sfu_per_core;
real scrb_wctl_per_core = pipeline_perf_if.sfu_uses[`SFU_WCTL]; int scrb_wctl_per_core;
real scrb_csrs_per_core = pipeline_perf_if.sfu_uses[`SFU_CSRS]; assign scrb_wctl_per_core = pipeline_perf_if.sfu_uses[`SFU_WCTL];
real sfu_tot = scrb_wctl_per_core+scrb_csrs_per_core; int scrb_csrs_per_core;
assign scrb_csrs_per_core = pipeline_perf_if.sfu_uses[`SFU_CSRS];
int sfu_tot;
assign sfu_tot = scrb_wctl_per_core+scrb_csrs_per_core;
always @(negedge busy) begin always @(negedge busy) begin
if (!reset) begin if (!reset) begin
@@ -372,16 +389,31 @@ module VX_core import VX_gpu_pkg::*; #(
$display("perf_dcache_wr_req_fire_r: %b", perf_dcache_wr_req_fire_r); $display("perf_dcache_wr_req_fire_r: %b", perf_dcache_wr_req_fire_r);
$display("perf_dcache_rsp_fire: %b", perf_dcache_rsp_fire); $display("perf_dcache_rsp_fire: %b", perf_dcache_rsp_fire);
$display("Instructions: %d, Cycles: %d, IPC: %f", commit_csr_if.instret, sched_csr_if.cycles, instrs/cycles); $display("Instructions: %d, Cycles: %d, IPC: %f", commit_csr_if.instret, sched_csr_if.cycles,
$display("scheduler idle: %d (%f)", pipeline_perf_if.sched_idles, scheduler_idles/cycles); $itor(instrs) / $itor(cycles));
$display("scheduler stalls: %d (%f)", pipeline_perf_if.sched_stalls, scheduler_stalls/cycles); $display("scheduler idle: %d cycles (%f%%)", pipeline_perf_if.sched_idles,
$display("ibuffer stalls: %d (%f)",pipeline_perf_if.ibf_stalls, ibuf_stalls/cycles); $itor(scheduler_idles) / $itor(cycles));
$display("issue stalls: %d(alu=%f, fpu=%f, lsu=%f, sfu=%f)",pipeline_perf_if.scb_stalls, scrb_alu_per_core/scrb_tot, scrb_fpu_per_core/scrb_tot, scrb_lsu_per_core/scrb_tot, scrb_sfu_per_core/scrb_tot); $display("scheduler stalls: %d cycles (%f%%)", pipeline_perf_if.sched_stalls,
$display("sfu stalls: %d (scrs=%f, wctl=%f)",pipeline_perf_if.units_uses[`EX_SFU], scrb_csrs_per_core/sfu_tot, scrb_wctl_per_core/sfu_tot); $itor(scheduler_stalls) / $itor(cycles));
$display("ibuffer stalls: %d cycles (%f%%)",pipeline_perf_if.ibf_stalls,
$itor(ibuf_stalls) / $itor(cycles));
// see VX_scoreboard.sv
$display("issue stalls: %d (ISSUE_WIDTH=%d) (alu=%f%%, fpu=%f%%, lsu=%f%%, sfu=%f%%)",
pipeline_perf_if.scb_stalls,
`ISSUE_WIDTH,
$itor(scrb_alu_per_core) / $itor(scrb_tot),
$itor(scrb_fpu_per_core) / $itor(scrb_tot),
$itor(scrb_lsu_per_core) / $itor(scrb_tot),
$itor(scrb_sfu_per_core) / $itor(scrb_tot));
$display("sfu stalls: %d (scrs=%f, wctl=%f)",pipeline_perf_if.units_uses[`EX_SFU],
$itor(scrb_csrs_per_core) / $itor(sfu_tot),
$itor(scrb_wctl_per_core) / $itor(sfu_tot));
$display("ifetches: %d", perf_ifetches); $display("ifetches: %d", perf_ifetches);
$display("ifetch latency: %f Cycles", icache_lat/ifetches); $display("ifetch latency: %f Cycles",
$itor(icache_lat) / $itor(ifetches));
$display("loads: %d", perf_loads); $display("loads: %d", perf_loads);
$display("load latency: %f Cycles", dcache_lat/loads); $display("load latency: %f Cycles",
$itor(dcache_lat) / $itor(loads));
$display("stores: %d", perf_stores); $display("stores: %d", perf_stores);
end end
end end

4
hw/rtl/core/VX_schedule.sv
View File

@@ -168,8 +168,8 @@ module VX_schedule import VX_gpu_pkg::*; #(
// back contains a valid id // back contains a valid id
if (gbar_bus_if.rsp_valid) begin if (gbar_bus_if.rsp_valid) begin
barrier_masks_n[gbar_bus_if.rsp_id] = '0; barrier_masks_n[gbar_bus_if.rsp_id] = '0;
// instead of unlocking all warps, only unlock those that requests // instead of unlocking all warps, only unlock those that
// for this barrier // requested this barrier
barrier_stalls_n &= ~barrier_masks[gbar_bus_if.rsp_id]; barrier_stalls_n &= ~barrier_masks[gbar_bus_if.rsp_id];
end end
`else `else