ram stdint + Quartus Files
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felsabbagh3
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|
|||||||
@@ -23,7 +23,7 @@ void vx_sq_mat_mult(void * x, void * y, void * z, unsigned mat_dim)
|
|||||||
off += 1;
|
off += 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
vx_printf("Offset: ", off);
|
// vx_printf("Offset: ", off);
|
||||||
|
|
||||||
|
|
||||||
mat_mult_args.offset = off;
|
mat_mult_args.offset = off;
|
||||||
|
|||||||
@@ -16,18 +16,7 @@ void vx_reschedule_warps()
|
|||||||
{
|
{
|
||||||
|
|
||||||
register unsigned curr_warp asm("s10");
|
register unsigned curr_warp asm("s10");
|
||||||
vx_printf("Reschedule: ", curr_warp);
|
// vx_printf("Reschedule: ", curr_warp);
|
||||||
asm __volatile__("nop");
|
|
||||||
asm __volatile__("nop");
|
|
||||||
asm __volatile__("nop");
|
|
||||||
asm __volatile__("nop");
|
|
||||||
asm __volatile__("nop");
|
|
||||||
asm __volatile__("nop");
|
|
||||||
asm __volatile__("nop");
|
|
||||||
asm __volatile__("nop");
|
|
||||||
asm __volatile__("nop");
|
|
||||||
asm __volatile__("nop");
|
|
||||||
asm __volatile__("nop");
|
|
||||||
asm __volatile__("nop");
|
asm __volatile__("nop");
|
||||||
|
|
||||||
if (queue_isEmpty(q+curr_warp))
|
if (queue_isEmpty(q+curr_warp))
|
||||||
@@ -131,20 +120,20 @@ void vx_spawnWarps(unsigned num_Warps, unsigned num_threads, FUNC, void * args)
|
|||||||
|
|
||||||
void vx_wait_for_warps(unsigned num_wait)
|
void vx_wait_for_warps(unsigned num_wait)
|
||||||
{
|
{
|
||||||
// vx_printf("wait for: ", num_wait);
|
vx_printf("wait for: ", num_wait);
|
||||||
unsigned num_available_warps = vx_available_warps();
|
unsigned num_available_warps = vx_available_warps();
|
||||||
unsigned num = 0;
|
unsigned num = 0;
|
||||||
while (num != num_wait)
|
while (num != num_wait)
|
||||||
{
|
{
|
||||||
num = 0;
|
num = 1;
|
||||||
for (int i = 0; i < num_available_warps; i++)
|
for (int i = 0; i < 32; i++)
|
||||||
{
|
{
|
||||||
if (done[i] == 1)
|
if (done[i] == 1)
|
||||||
{
|
{
|
||||||
num += 1;
|
num += 1;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
// vx_printf("Found: ", num);
|
vx_printf("Found: ", num);
|
||||||
}
|
}
|
||||||
|
|
||||||
// vx_printf("num found: ", num);
|
// vx_printf("num found: ", num);
|
||||||
|
|||||||
BIN
rtl/.DS_Store
vendored
Normal file
BIN
rtl/.DS_Store
vendored
Normal file
Binary file not shown.
@@ -3,7 +3,9 @@
|
|||||||
module VX_csr_handler (
|
module VX_csr_handler (
|
||||||
input wire clk,
|
input wire clk,
|
||||||
input wire[11:0] in_decode_csr_address, // done
|
input wire[11:0] in_decode_csr_address, // done
|
||||||
|
/* verilator lint_off UNUSED */
|
||||||
input wire[11:0] in_mem_csr_address,
|
input wire[11:0] in_mem_csr_address,
|
||||||
|
/* verilator lint_on UNUSED */
|
||||||
input wire in_mem_is_csr,
|
input wire in_mem_is_csr,
|
||||||
/* verilator lint_off UNUSED */
|
/* verilator lint_off UNUSED */
|
||||||
input wire[31:0] in_mem_csr_result,
|
input wire[31:0] in_mem_csr_result,
|
||||||
@@ -13,7 +15,7 @@ module VX_csr_handler (
|
|||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
reg[11:0] csr[4095:0];
|
reg[11:0] csr[1024:0];
|
||||||
reg[63:0] cycle;
|
reg[63:0] cycle;
|
||||||
reg[63:0] instret;
|
reg[63:0] instret;
|
||||||
reg[11:0] decode_csr_address;
|
reg[11:0] decode_csr_address;
|
||||||
@@ -42,7 +44,9 @@ module VX_csr_handler (
|
|||||||
|
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
if(in_mem_is_csr) begin
|
if(in_mem_is_csr) begin
|
||||||
|
/* verilator lint_off WIDTH */
|
||||||
csr[in_mem_csr_address] <= in_mem_csr_result[11:0];
|
csr[in_mem_csr_address] <= in_mem_csr_result[11:0];
|
||||||
|
/* verilator lint_on WIDTH */
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
@@ -53,11 +57,13 @@ module VX_csr_handler (
|
|||||||
assign read_instreth = decode_csr_address == 12'hC82;
|
assign read_instreth = decode_csr_address == 12'hC82;
|
||||||
|
|
||||||
|
|
||||||
|
/* verilator lint_off WIDTH */
|
||||||
assign out_decode_csr_data = read_cycle ? cycle[31:0] :
|
assign out_decode_csr_data = read_cycle ? cycle[31:0] :
|
||||||
read_cycleh ? cycle[63:32] :
|
read_cycleh ? cycle[63:32] :
|
||||||
read_instret ? instret[31:0] :
|
read_instret ? instret[31:0] :
|
||||||
read_instreth ? instret[63:32] :
|
read_instreth ? instret[63:32] :
|
||||||
{{20{1'b0}}, csr[decode_csr_address]};
|
{{20{1'b0}}, csr[decode_csr_address]};
|
||||||
|
/* verilator lint_on WIDTH */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@@ -3,8 +3,10 @@
|
|||||||
`define NT 4
|
`define NT 4
|
||||||
`define NT_M1 (`NT-1)
|
`define NT_M1 (`NT-1)
|
||||||
|
|
||||||
|
// NW_M1 is actually log2(NW)
|
||||||
`define NW_M1 3
|
`define NW_M1 3
|
||||||
`define NW 8
|
`define NW 8
|
||||||
|
// Uncomment the below line if NW=1
|
||||||
// `define ONLY
|
// `define ONLY
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@@ -40,22 +40,22 @@ module VX_fetch (
|
|||||||
reg[`NW_M1:0] warp_state;
|
reg[`NW_M1:0] warp_state;
|
||||||
reg[`NW_M1:0] warp_count;
|
reg[`NW_M1:0] warp_count;
|
||||||
|
|
||||||
reg[31:0] num_ecalls;
|
// reg[31:0] num_ecalls;
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
warp_num = 0;
|
warp_num = 0;
|
||||||
warp_state = 0;
|
warp_state = 0;
|
||||||
num_ecalls = 0;
|
// num_ecalls = 0;
|
||||||
warp_count = 1;
|
warp_count = 1;
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
||||||
always @(posedge clk) begin
|
// always @(posedge clk) begin
|
||||||
if (in_ebreak) begin
|
// if (in_ebreak) begin
|
||||||
num_ecalls <= num_ecalls + 1;
|
// num_ecalls <= num_ecalls + 1;
|
||||||
$display("--------> New num_ecalls = %h", num_ecalls+1);
|
// $display("--------> New num_ecalls = %h", num_ecalls+1);
|
||||||
end
|
// end
|
||||||
end
|
// end
|
||||||
|
|
||||||
wire add_warp = in_wspawn && !in_ebreak && !in_clone_stall;
|
wire add_warp = in_wspawn && !in_ebreak && !in_clone_stall;
|
||||||
wire remove_warp = in_ebreak && !in_wspawn && !in_clone_stall;
|
wire remove_warp = in_ebreak && !in_wspawn && !in_clone_stall;
|
||||||
@@ -65,7 +65,7 @@ module VX_fetch (
|
|||||||
warp_num <= 0;
|
warp_num <= 0;
|
||||||
`ifndef ONLY
|
`ifndef ONLY
|
||||||
end else if (!warp_glob_valid[warp_num+1]) begin
|
end else if (!warp_glob_valid[warp_num+1]) begin
|
||||||
$display("Skipping one");
|
// $display("Skipping one");
|
||||||
warp_num <= warp_num + 2;
|
warp_num <= warp_num + 2;
|
||||||
`endif
|
`endif
|
||||||
end else begin
|
end else begin
|
||||||
@@ -75,12 +75,12 @@ module VX_fetch (
|
|||||||
if (add_warp) begin
|
if (add_warp) begin
|
||||||
warp_state <= warp_state + 1;
|
warp_state <= warp_state + 1;
|
||||||
warp_count <= warp_count + 1;
|
warp_count <= warp_count + 1;
|
||||||
$display("Adding a new warp %h", warp_state+1);
|
// $display("Adding a new warp %h", warp_state+1);
|
||||||
end else if (remove_warp) begin // No removing, just invalidating
|
end else if (remove_warp) begin // No removing, just invalidating
|
||||||
warp_count <= warp_count - 1;
|
warp_count <= warp_count - 1;
|
||||||
$display("Removing a warp %h %h", in_decode_warp_num, warp_count);
|
// $display("Removing a warp %h %h", in_decode_warp_num, warp_count);
|
||||||
if (warp_count == 2) begin
|
if (warp_count == 2) begin
|
||||||
$display("&&&&&&&&&&&&& STATE 0");
|
// $display("&&&&&&&&&&&&& STATE 0");
|
||||||
warp_state <= 0;
|
warp_state <= 0;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
@@ -103,9 +103,9 @@ module VX_fetch (
|
|||||||
wire[31:0] warp_zero_wspawn_pc = in_wspawn_pc;
|
wire[31:0] warp_zero_wspawn_pc = in_wspawn_pc;
|
||||||
wire warp_zero_remove = remove_warp && (in_decode_warp_num == 0);
|
wire warp_zero_remove = remove_warp && (in_decode_warp_num == 0);
|
||||||
|
|
||||||
always @(*) begin : proc_
|
// always @(*) begin : proc_
|
||||||
if (warp_zero_remove) $display("4Removing warp: %h", 0);
|
// if (warp_zero_remove) $display("4Removing warp: %h", 0);
|
||||||
end
|
// end
|
||||||
|
|
||||||
VX_warp VX_Warp(
|
VX_warp VX_Warp(
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
@@ -140,9 +140,9 @@ module VX_fetch (
|
|||||||
wire[31:0] warp_zero_wspawn_pc = in_wspawn_pc;
|
wire[31:0] warp_zero_wspawn_pc = in_wspawn_pc;
|
||||||
wire warp_zero_remove = remove_warp && (in_decode_warp_num == cur_warp);
|
wire warp_zero_remove = remove_warp && (in_decode_warp_num == cur_warp);
|
||||||
|
|
||||||
always @(*) begin : proc_
|
// always @(*) begin : proc_
|
||||||
if (warp_zero_remove) $display("4Removing warp: %h", cur_warp);
|
// if (warp_zero_remove) $display("4Removing warp: %h", cur_warp);
|
||||||
end
|
// end
|
||||||
|
|
||||||
VX_warp VX_Warp(
|
VX_warp VX_Warp(
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
@@ -184,11 +184,11 @@ module VX_fetch (
|
|||||||
assign out_PC = out_PC_var;
|
assign out_PC = out_PC_var;
|
||||||
assign out_valid = out_valid_var;
|
assign out_valid = out_valid_var;
|
||||||
|
|
||||||
always @(*) begin
|
// always @(*) begin
|
||||||
if (out_valid[0]) begin
|
// if (out_valid[0]) begin
|
||||||
$display("[%d] %h #%b#",out_warp_num, out_PC, out_valid);
|
// $display("[%d] %h #%b#",out_warp_num, out_PC, out_valid);
|
||||||
end
|
// end
|
||||||
end
|
// end
|
||||||
|
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
|
|||||||
@@ -1,7 +1,7 @@
|
|||||||
|
|
||||||
`include "VX_define.v"
|
`include "VX_define.v"
|
||||||
|
|
||||||
|
// Old SM file
|
||||||
|
|
||||||
module VX_shared_memory(
|
module VX_shared_memory(
|
||||||
input wire clk,
|
input wire clk,
|
||||||
|
|||||||
30
rtl/Vortex.qpf
Normal file
30
rtl/Vortex.qpf
Normal file
@@ -0,0 +1,30 @@
|
|||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||||
|
# Your use of Intel Corporation's design tools, logic functions
|
||||||
|
# and other software and tools, and its AMPP partner logic
|
||||||
|
# functions, and any output files from any of the foregoing
|
||||||
|
# (including device programming or simulation files), and any
|
||||||
|
# associated documentation or information are expressly subject
|
||||||
|
# to the terms and conditions of the Intel Program License
|
||||||
|
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
|
# the Intel FPGA IP License Agreement, or other applicable license
|
||||||
|
# agreement, including, without limitation, that your use is for
|
||||||
|
# the sole purpose of programming logic devices manufactured by
|
||||||
|
# Intel and sold by Intel or its authorized distributors. Please
|
||||||
|
# refer to the applicable agreement for further details.
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Quartus Prime
|
||||||
|
# Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition
|
||||||
|
# Date created = 20:33:29 May 12, 2019
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
|
||||||
|
QUARTUS_VERSION = "18.0"
|
||||||
|
DATE = "20:33:29 May 12, 2019"
|
||||||
|
|
||||||
|
# Revisions
|
||||||
|
|
||||||
|
PROJECT_REVISION = "Vortex"
|
||||||
47
rtl/Vortex.qsf
Normal file
47
rtl/Vortex.qsf
Normal file
@@ -0,0 +1,47 @@
|
|||||||
|
set_global_assignment -name FAMILY "Arria 10"
|
||||||
|
set_global_assignment -name TOP_LEVEL_ENTITY Vortex
|
||||||
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0
|
||||||
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:33:29 MAY 12, 2019"
|
||||||
|
set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Pro Edition"
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/Vortex.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_alu.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_context.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_context_slave.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_csr_handler.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_d_e_reg.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_decode.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_define.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_e_m_reg.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_execute.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_f_d_reg.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_fetch.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_forwarding.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_m_w_reg.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_memory.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_register_file.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_register_file_master_slave.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_register_file_slave.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_warp.v
|
||||||
|
set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_writeback.v
|
||||||
|
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||||
|
set_global_assignment -name DEVICE 10AX115U3F45I2SG
|
||||||
|
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 4
|
||||||
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
|
||||||
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
|
||||||
|
set_global_assignment -name POWER_AUTO_COMPUTE_TJ ON
|
||||||
|
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||||
|
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||||
|
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 50000
|
||||||
|
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
|
||||||
|
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||||
|
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
|
||||||
|
set_global_assignment -name SDC_FILE clk_const.sdc
|
||||||
|
set_global_assignment -name ALLOW_REGISTER_RETIMING OFF
|
||||||
|
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
|
||||||
|
set_global_assignment -name AUTO_ROM_RECOGNITION OFF
|
||||||
|
set_global_assignment -name AUTO_RAM_RECOGNITION OFF
|
||||||
|
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
|
||||||
|
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS ON
|
||||||
|
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF
|
||||||
|
set_global_assignment -name FLOW_DISABLE_ASSEMBLER ON
|
||||||
|
set_instance_assignment -name PARTITION_COLOUR 4288217044 -to Vortex -entity Vortex
|
||||||
1
rtl/clk_const.sdc
Normal file
1
rtl/clk_const.sdc
Normal file
@@ -0,0 +1 @@
|
|||||||
|
create_clock -name {clk} -period "400 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]
|
||||||
BIN
rtl/obj_dir/VVortex
Executable file
BIN
rtl/obj_dir/VVortex
Executable file
Binary file not shown.
14783
rtl/obj_dir/VVortex.cpp
Normal file
14783
rtl/obj_dir/VVortex.cpp
Normal file
File diff suppressed because it is too large
Load Diff
489
rtl/obj_dir/VVortex.h
Normal file
489
rtl/obj_dir/VVortex.h
Normal file
@@ -0,0 +1,489 @@
|
|||||||
|
// Verilated -*- C++ -*-
|
||||||
|
// DESCRIPTION: Verilator output: Primary design header
|
||||||
|
//
|
||||||
|
// This header should be included by all source files instantiating the design.
|
||||||
|
// The class here is then constructed to instantiate the design.
|
||||||
|
// See the Verilator manual for examples.
|
||||||
|
|
||||||
|
#ifndef _VVortex_H_
|
||||||
|
#define _VVortex_H_
|
||||||
|
|
||||||
|
#include "verilated.h"
|
||||||
|
|
||||||
|
class VVortex__Syms;
|
||||||
|
class VVortex_VX_context_slave;
|
||||||
|
|
||||||
|
//----------
|
||||||
|
|
||||||
|
VL_MODULE(VVortex) {
|
||||||
|
public:
|
||||||
|
// CELLS
|
||||||
|
// Public to allow access to /*verilator_public*/ items;
|
||||||
|
// otherwise the application code can consider these internals.
|
||||||
|
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one;
|
||||||
|
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one;
|
||||||
|
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one;
|
||||||
|
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one;
|
||||||
|
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one;
|
||||||
|
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one;
|
||||||
|
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one;
|
||||||
|
|
||||||
|
// PORTS
|
||||||
|
// The application code writes and reads these signals to
|
||||||
|
// propagate new values into/out from the Verilated model.
|
||||||
|
// Begin mtask footprint all:
|
||||||
|
VL_IN8(clk,0,0);
|
||||||
|
VL_IN8(reset,0,0);
|
||||||
|
VL_OUT8(out_cache_driver_in_mem_read,2,0);
|
||||||
|
VL_OUT8(out_cache_driver_in_mem_write,2,0);
|
||||||
|
VL_OUT8(out_ebreak,0,0);
|
||||||
|
VL_IN(fe_instruction,31,0);
|
||||||
|
VL_OUT(curr_PC,31,0);
|
||||||
|
VL_IN(in_cache_driver_out_data[4],31,0);
|
||||||
|
VL_OUT(out_cache_driver_in_address[4],31,0);
|
||||||
|
VL_OUT8(out_cache_driver_in_valid[4],0,0);
|
||||||
|
VL_OUT(out_cache_driver_in_data[4],31,0);
|
||||||
|
|
||||||
|
// LOCAL SIGNALS
|
||||||
|
// Internals; generally not touched by application code
|
||||||
|
// Anonymous structures to workaround compiler member-count bugs
|
||||||
|
struct {
|
||||||
|
// Begin mtask footprint all:
|
||||||
|
VL_SIG8(Vortex__DOT__decode_branch_stall,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__decode_branch_type,2,0);
|
||||||
|
VL_SIG8(Vortex__DOT__decode_jal,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__decode_change_mask,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__execute_branch_stall,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__memory_branch_dir,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__forwarding_src1_fwd,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__forwarding_src2_fwd,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_num,3,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_state,3,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_count,3,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__add_warp,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__remove_warp,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_change_mask,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_stall,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_change_mask,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_stall,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_change_mask,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_stall,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_change_mask,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_stall,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_change_mask,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_stall,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_change_mask,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_stall,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_change_mask,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_stall,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_change_mask,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_stall,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__warp_num,3,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_clone,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jalrs,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jmprt,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_wspawn,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__jal_sys_jal,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__real_zero_isclone,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__temp_out_clone_stall,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_ebreak,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__temp_final_alu,4,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_wspawn,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_isclone,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_wspawn,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_isclone,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_wspawn,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_isclone,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_wspawn,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_isclone,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_wspawn,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_isclone,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_wspawn,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_isclone,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_wspawn,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_isclone,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall,5,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rd,4,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__alu_op,4,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__wb,1,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rs2_src,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__mem_read,2,0);
|
||||||
|
};
|
||||||
|
struct {
|
||||||
|
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__mem_write,2,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__branch_type,2,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__is_csr,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__jal,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__warp_num,3,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__stalling,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__rd,4,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__wb,1,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__mem_read,2,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__mem_write,2,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__is_csr,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__branch_type,2,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__jal,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__warp_num,3,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__rd,4,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__wb,1,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__warp_num,3,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd,0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd,0,0);
|
||||||
|
VL_SIG16(Vortex__DOT__decode_csr_address,11,0);
|
||||||
|
VL_SIG16(Vortex__DOT__vx_decode__DOT__alu_tempp,11,0);
|
||||||
|
VL_SIG16(Vortex__DOT__vx_d_e_reg__DOT__csr_address,11,0);
|
||||||
|
VL_SIG16(Vortex__DOT__vx_e_m_reg__DOT__csr_address,11,0);
|
||||||
|
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__decode_csr_address,11,0);
|
||||||
|
VL_SIG(Vortex__DOT__decode_itype_immed,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__decode_jal_offset,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__memory_branch_dest,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__csr_decode_csr_data,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__out_PC_var,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__instruction,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__curr_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__upper_immed,19,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__curr_PC,31,0);
|
||||||
|
};
|
||||||
|
struct {
|
||||||
|
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__branch_offset,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__jal_dest,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0);
|
||||||
|
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
|
||||||
|
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
|
||||||
|
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
|
||||||
|
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
|
||||||
|
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
|
||||||
|
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
|
||||||
|
VL_SIG8(Vortex__DOT__fetch_valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__f_d_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__decode_a_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__decode_b_reg_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__decode_valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__decode_thread_mask[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__d_e_a_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__d_e_b_reg_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__d_e_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__execute_alu_result[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__execute_b_reg_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__execute_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__e_m_alu_result[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__e_m_b_reg_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__e_m_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__memory_alu_result[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__memory_mem_result[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__memory_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__m_w_alu_result[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__m_w_mem_result[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__m_w_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__writeback_write_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_fetch__DOT__warp_glob_pc[8],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_glob_valid[8][4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__out_valid_var[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__w0_t0_registers[32],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__glob_a_reg_data[8][4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__glob_b_reg_data[8][4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__glob_clone_stall[8],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[32],31,0);
|
||||||
|
};
|
||||||
|
struct {
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers[32],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[4],31,0);
|
||||||
|
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[1025],11,0);
|
||||||
|
};
|
||||||
|
|
||||||
|
// LOCAL VARIABLES
|
||||||
|
// Internals; generally not touched by application code
|
||||||
|
// Anonymous structures to workaround compiler member-count bugs
|
||||||
|
struct {
|
||||||
|
// Begin mtask footprint all:
|
||||||
|
VL_SIG8(__Vtableidx1,2,0);
|
||||||
|
VL_SIG8(__Vclklast__TOP__clk,0,0);
|
||||||
|
VL_SIG8(__Vclklast__TOP__reset,0,0);
|
||||||
|
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT____Vlvbound1,11,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result,31,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_thread_mask[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[4],31,0);
|
||||||
|
};
|
||||||
|
struct {
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__0__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__0__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[32],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data[4],31,0);
|
||||||
|
};
|
||||||
|
struct {
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0);
|
||||||
|
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid[4],0,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[32],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
|
||||||
|
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
|
||||||
|
};
|
||||||
|
static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);
|
||||||
|
|
||||||
|
// INTERNAL VARIABLES
|
||||||
|
// Internals; generally not touched by application code
|
||||||
|
VVortex__Syms* __VlSymsp; // Symbol table
|
||||||
|
|
||||||
|
// PARAMETERS
|
||||||
|
// Parameters marked /*verilator public*/ for use by application code
|
||||||
|
|
||||||
|
// CONSTRUCTORS
|
||||||
|
private:
|
||||||
|
VL_UNCOPYABLE(VVortex); ///< Copying not allowed
|
||||||
|
public:
|
||||||
|
/// Construct the model; called by application code
|
||||||
|
/// The special name may be used to make a wrapper with a
|
||||||
|
/// single model invisible with respect to DPI scope names.
|
||||||
|
VVortex(const char* name="TOP");
|
||||||
|
/// Destroy the model; called (often implicitly) by application code
|
||||||
|
~VVortex();
|
||||||
|
|
||||||
|
// API METHODS
|
||||||
|
/// Evaluate the model. Application must call when inputs change.
|
||||||
|
void eval();
|
||||||
|
/// Simulation complete, run final blocks. Application must call on completion.
|
||||||
|
void final();
|
||||||
|
|
||||||
|
// INTERNAL METHODS
|
||||||
|
private:
|
||||||
|
static void _eval_initial_loop(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
public:
|
||||||
|
void __Vconfigure(VVortex__Syms* symsp, bool first);
|
||||||
|
private:
|
||||||
|
static QData _change_request(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
public:
|
||||||
|
static void _combo__TOP__10(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
static void _combo__TOP__8(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
private:
|
||||||
|
void _ctor_var_reset();
|
||||||
|
public:
|
||||||
|
static void _eval(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
private:
|
||||||
|
#ifdef VL_DEBUG
|
||||||
|
void _eval_debug_assertions();
|
||||||
|
#endif // VL_DEBUG
|
||||||
|
public:
|
||||||
|
static void _eval_initial(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
static void _eval_settle(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
static void _initial__TOP__1(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
static void _sequent__TOP__4(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
static void _sequent__TOP__5(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
static void _sequent__TOP__6(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
static void _sequent__TOP__7(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
static void _sequent__TOP__9(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
static void _settle__TOP__2(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
static void _settle__TOP__3(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
} VL_ATTR_ALIGNED(128);
|
||||||
|
|
||||||
|
#endif // guard
|
||||||
66
rtl/obj_dir/VVortex.mk
Normal file
66
rtl/obj_dir/VVortex.mk
Normal file
@@ -0,0 +1,66 @@
|
|||||||
|
# Verilated -*- Makefile -*-
|
||||||
|
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
|
||||||
|
#
|
||||||
|
# Execute this makefile from the object directory:
|
||||||
|
# make -f VVortex.mk
|
||||||
|
|
||||||
|
default: VVortex
|
||||||
|
|
||||||
|
### Constants...
|
||||||
|
# Perl executable (from $PERL)
|
||||||
|
PERL = perl
|
||||||
|
# Path to Verilator kit (from $VERILATOR_ROOT)
|
||||||
|
VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator
|
||||||
|
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
|
||||||
|
SYSTEMC_INCLUDE ?=
|
||||||
|
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
|
||||||
|
SYSTEMC_LIBDIR ?=
|
||||||
|
|
||||||
|
### Switches...
|
||||||
|
# SystemC output mode? 0/1 (from --sc)
|
||||||
|
VM_SC = 0
|
||||||
|
# Legacy or SystemC output mode? 0/1 (from --sc)
|
||||||
|
VM_SP_OR_SC = $(VM_SC)
|
||||||
|
# Deprecated
|
||||||
|
VM_PCLI = 1
|
||||||
|
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
|
||||||
|
VM_SC_TARGET_ARCH = linux
|
||||||
|
|
||||||
|
### Vars...
|
||||||
|
# Design prefix (from --prefix)
|
||||||
|
VM_PREFIX = VVortex
|
||||||
|
# Module prefix (from --prefix)
|
||||||
|
VM_MODPREFIX = VVortex
|
||||||
|
# User CFLAGS (from -CFLAGS on Verilator command line)
|
||||||
|
VM_USER_CFLAGS = \
|
||||||
|
|
||||||
|
# User LDLIBS (from -LDFLAGS on Verilator command line)
|
||||||
|
VM_USER_LDLIBS = \
|
||||||
|
|
||||||
|
# User .cpp files (from .cpp's on Verilator command line)
|
||||||
|
VM_USER_CLASSES = \
|
||||||
|
test_bench \
|
||||||
|
|
||||||
|
# User .cpp directories (from .cpp's on Verilator command line)
|
||||||
|
VM_USER_DIR = \
|
||||||
|
. \
|
||||||
|
|
||||||
|
|
||||||
|
### Default rules...
|
||||||
|
# Include list of all generated classes
|
||||||
|
include VVortex_classes.mk
|
||||||
|
# Include global rules
|
||||||
|
include $(VERILATOR_ROOT)/include/verilated.mk
|
||||||
|
|
||||||
|
### Executable rules... (from --exe)
|
||||||
|
VPATH += $(VM_USER_DIR)
|
||||||
|
|
||||||
|
test_bench.o: test_bench.cpp
|
||||||
|
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
|
||||||
|
|
||||||
|
### Link rules... (from --exe)
|
||||||
|
VVortex: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
|
||||||
|
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS)
|
||||||
|
|
||||||
|
|
||||||
|
# Verilated -*- Makefile -*-
|
||||||
8879
rtl/obj_dir/VVortex_VX_context_slave.cpp
Normal file
8879
rtl/obj_dir/VVortex_VX_context_slave.cpp
Normal file
File diff suppressed because it is too large
Load Diff
257
rtl/obj_dir/VVortex_VX_context_slave.h
Normal file
257
rtl/obj_dir/VVortex_VX_context_slave.h
Normal file
@@ -0,0 +1,257 @@
|
|||||||
|
// Verilated -*- C++ -*-
|
||||||
|
// DESCRIPTION: Verilator output: Design internal header
|
||||||
|
// See VVortex.h for the primary calling header
|
||||||
|
|
||||||
|
#ifndef _VVortex_VX_context_slave_H_
|
||||||
|
#define _VVortex_VX_context_slave_H_
|
||||||
|
|
||||||
|
#include "verilated.h"
|
||||||
|
|
||||||
|
class VVortex__Syms;
|
||||||
|
|
||||||
|
//----------
|
||||||
|
|
||||||
|
VL_MODULE(VVortex_VX_context_slave) {
|
||||||
|
public:
|
||||||
|
|
||||||
|
// PORTS
|
||||||
|
// Begin mtask footprint all:
|
||||||
|
VL_IN8(clk,0,0);
|
||||||
|
VL_IN8(in_warp,0,0);
|
||||||
|
VL_IN8(in_wb_warp,0,0);
|
||||||
|
VL_IN8(in_write_register,0,0);
|
||||||
|
VL_IN8(in_rd,4,0);
|
||||||
|
VL_IN8(in_src1,4,0);
|
||||||
|
VL_IN8(in_src2,4,0);
|
||||||
|
VL_IN8(in_is_clone,0,0);
|
||||||
|
VL_IN8(in_is_jal,0,0);
|
||||||
|
VL_IN8(in_src1_fwd,0,0);
|
||||||
|
VL_IN8(in_src2_fwd,0,0);
|
||||||
|
VL_IN8(in_wspawn,0,0);
|
||||||
|
VL_OUT8(out_clone_stall,0,0);
|
||||||
|
VL_IN(in_curr_PC,31,0);
|
||||||
|
VL_IN8(in_valid[4],0,0);
|
||||||
|
VL_IN(in_write_data[4],31,0);
|
||||||
|
VL_IN(in_src1_fwd_data[4],31,0);
|
||||||
|
VL_IN(in_src2_fwd_data[4],31,0);
|
||||||
|
VL_IN(in_wspawn_regs[32],31,0);
|
||||||
|
VL_OUT(out_a_reg_data[4],31,0);
|
||||||
|
VL_OUT(out_b_reg_data[4],31,0);
|
||||||
|
|
||||||
|
// LOCAL SIGNALS
|
||||||
|
// Begin mtask footprint all:
|
||||||
|
VL_SIG8(__PVT__clone_state_stall,5,0);
|
||||||
|
VL_SIG8(__PVT__wspawn_state_stall,5,0);
|
||||||
|
VL_SIG(__PVT__rd1_register[4],31,0);
|
||||||
|
VL_SIG(__PVT__rd2_register[4],31,0);
|
||||||
|
VL_SIG(__PVT__clone_regsiters[32],31,0);
|
||||||
|
VL_SIG(__PVT__vx_register_file_master__DOT__registers[32],31,0);
|
||||||
|
VL_SIG(__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
|
||||||
|
VL_SIG(__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
|
||||||
|
VL_SIG(__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
|
||||||
|
|
||||||
|
// LOCAL VARIABLES
|
||||||
|
// Anonymous structures to workaround compiler member-count bugs
|
||||||
|
struct {
|
||||||
|
// Begin mtask footprint all:
|
||||||
|
VL_SIG8(__Vdly__clone_state_stall,5,0);
|
||||||
|
VL_SIG8(__Vdly__wspawn_state_stall,5,0);
|
||||||
|
VL_SIG8(__Vdlyvdim0__vx_register_file_master__DOT__registers__v0,4,0);
|
||||||
|
VL_SIG8(__Vdlyvset__vx_register_file_master__DOT__registers__v0,0,0);
|
||||||
|
VL_SIG8(__Vdlyvset__vx_register_file_master__DOT__registers__v1,0,0);
|
||||||
|
VL_SIG8(__Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,4,0);
|
||||||
|
VL_SIG8(__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,0,0);
|
||||||
|
VL_SIG8(__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1,0,0);
|
||||||
|
VL_SIG8(__Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0,4,0);
|
||||||
|
VL_SIG8(__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0,0,0);
|
||||||
|
VL_SIG8(__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1,0,0);
|
||||||
|
VL_SIG8(__Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0,4,0);
|
||||||
|
VL_SIG8(__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0,0,0);
|
||||||
|
VL_SIG8(__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1,0,0);
|
||||||
|
VL_SIG(__Vcellout__vx_register_file_master__out_src2_data,31,0);
|
||||||
|
VL_SIG(__Vcellout__vx_register_file_master__out_src1_data,31,0);
|
||||||
|
VL_SIG(__Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||||
|
VL_SIG(__Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||||
|
VL_SIG(__Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||||
|
VL_SIG(__Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||||
|
VL_SIG(__Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||||
|
VL_SIG(__Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v0,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v1,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v2,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v3,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v4,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v5,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v6,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v7,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v8,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v9,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v10,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v11,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v12,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v13,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v14,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v15,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v16,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v17,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v18,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v19,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v20,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v21,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v22,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v23,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v24,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v25,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v26,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v27,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v28,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v29,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v30,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v31,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v32,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8,31,0);
|
||||||
|
};
|
||||||
|
struct {
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6,31,0);
|
||||||
|
};
|
||||||
|
struct {
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31,31,0);
|
||||||
|
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32,31,0);
|
||||||
|
VL_SIG(__Vcellout__vx_register_file_master__out_regs[32],31,0);
|
||||||
|
VL_SIG(__Vcellinp__vx_register_file_master__in_wspawn_regs[32],31,0);
|
||||||
|
VL_SIG(__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
|
||||||
|
VL_SIG(__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
|
||||||
|
VL_SIG(__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
|
||||||
|
};
|
||||||
|
|
||||||
|
// INTERNAL VARIABLES
|
||||||
|
private:
|
||||||
|
VVortex__Syms* __VlSymsp; // Symbol table
|
||||||
|
public:
|
||||||
|
|
||||||
|
// PARAMETERS
|
||||||
|
|
||||||
|
// CONSTRUCTORS
|
||||||
|
private:
|
||||||
|
VL_UNCOPYABLE(VVortex_VX_context_slave); ///< Copying not allowed
|
||||||
|
public:
|
||||||
|
VVortex_VX_context_slave(const char* name="TOP");
|
||||||
|
~VVortex_VX_context_slave();
|
||||||
|
|
||||||
|
// API METHODS
|
||||||
|
|
||||||
|
// INTERNAL METHODS
|
||||||
|
void __Vconfigure(VVortex__Syms* symsp, bool first);
|
||||||
|
void _combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__29(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
void _combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__36(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
private:
|
||||||
|
void _ctor_var_reset();
|
||||||
|
public:
|
||||||
|
void _initial__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__1(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__15(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__22(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one__16(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one__17(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one__18(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one__19(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one__20(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one__21(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
void _settle__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__8(VVortex__Syms* __restrict vlSymsp);
|
||||||
|
} VL_ATTR_ALIGNED(128);
|
||||||
|
|
||||||
|
#endif // guard
|
||||||
BIN
rtl/obj_dir/VVortex__ALL.a
Normal file
BIN
rtl/obj_dir/VVortex__ALL.a
Normal file
Binary file not shown.
4
rtl/obj_dir/VVortex__ALLcls.cpp
Normal file
4
rtl/obj_dir/VVortex__ALLcls.cpp
Normal file
@@ -0,0 +1,4 @@
|
|||||||
|
// DESCRIPTION: Generated by verilator_includer via makefile
|
||||||
|
#define VL_INCLUDE_OPT include
|
||||||
|
#include "VVortex.cpp"
|
||||||
|
#include "VVortex_VX_context_slave.cpp"
|
||||||
5
rtl/obj_dir/VVortex__ALLcls.d
Normal file
5
rtl/obj_dir/VVortex__ALLcls.d
Normal file
@@ -0,0 +1,5 @@
|
|||||||
|
VVortex__ALLcls.o: VVortex__ALLcls.cpp VVortex.cpp VVortex.h \
|
||||||
|
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
|
||||||
|
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
|
||||||
|
VVortex__Syms.h VVortex_VX_context_slave.h \
|
||||||
|
VVortex_VX_context_slave.cpp
|
||||||
BIN
rtl/obj_dir/VVortex__ALLcls.o
Normal file
BIN
rtl/obj_dir/VVortex__ALLcls.o
Normal file
Binary file not shown.
3
rtl/obj_dir/VVortex__ALLsup.cpp
Normal file
3
rtl/obj_dir/VVortex__ALLsup.cpp
Normal file
@@ -0,0 +1,3 @@
|
|||||||
|
// DESCRIPTION: Generated by verilator_includer via makefile
|
||||||
|
#define VL_INCLUDE_OPT include
|
||||||
|
#include "VVortex__Syms.cpp"
|
||||||
4
rtl/obj_dir/VVortex__ALLsup.d
Normal file
4
rtl/obj_dir/VVortex__ALLsup.d
Normal file
@@ -0,0 +1,4 @@
|
|||||||
|
VVortex__ALLsup.o: VVortex__ALLsup.cpp VVortex__Syms.cpp VVortex__Syms.h \
|
||||||
|
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
|
||||||
|
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
|
||||||
|
VVortex.h VVortex_VX_context_slave.h
|
||||||
BIN
rtl/obj_dir/VVortex__ALLsup.o
Normal file
BIN
rtl/obj_dir/VVortex__ALLsup.o
Normal file
Binary file not shown.
41
rtl/obj_dir/VVortex__Syms.cpp
Normal file
41
rtl/obj_dir/VVortex__Syms.cpp
Normal file
@@ -0,0 +1,41 @@
|
|||||||
|
// Verilated -*- C++ -*-
|
||||||
|
// DESCRIPTION: Verilator output: Symbol table implementation internals
|
||||||
|
|
||||||
|
#include "VVortex__Syms.h"
|
||||||
|
#include "VVortex.h"
|
||||||
|
#include "VVortex_VX_context_slave.h"
|
||||||
|
|
||||||
|
// FUNCTIONS
|
||||||
|
VVortex__Syms::VVortex__Syms(VVortex* topp, const char* namep)
|
||||||
|
// Setup locals
|
||||||
|
: __Vm_namep(namep)
|
||||||
|
, __Vm_didInit(false)
|
||||||
|
// Setup submodule names
|
||||||
|
, TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[1].VX_Context_one"))
|
||||||
|
, TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[2].VX_Context_one"))
|
||||||
|
, TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[3].VX_Context_one"))
|
||||||
|
, TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[4].VX_Context_one"))
|
||||||
|
, TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[5].VX_Context_one"))
|
||||||
|
, TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[6].VX_Context_one"))
|
||||||
|
, TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[7].VX_Context_one"))
|
||||||
|
{
|
||||||
|
// Pointer to top level
|
||||||
|
TOPp = topp;
|
||||||
|
// Setup each module's pointers to their submodules
|
||||||
|
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one;
|
||||||
|
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one;
|
||||||
|
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one;
|
||||||
|
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one;
|
||||||
|
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one;
|
||||||
|
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one;
|
||||||
|
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one;
|
||||||
|
// Setup each module's pointer back to symbol table (for public functions)
|
||||||
|
TOPp->__Vconfigure(this, true);
|
||||||
|
TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.__Vconfigure(this, true);
|
||||||
|
TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||||
|
TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||||
|
TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||||
|
TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||||
|
TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||||
|
TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||||
|
}
|
||||||
42
rtl/obj_dir/VVortex__Syms.h
Normal file
42
rtl/obj_dir/VVortex__Syms.h
Normal file
@@ -0,0 +1,42 @@
|
|||||||
|
// Verilated -*- C++ -*-
|
||||||
|
// DESCRIPTION: Verilator output: Symbol table internal header
|
||||||
|
//
|
||||||
|
// Internal details; most calling programs do not need this header
|
||||||
|
|
||||||
|
#ifndef _VVortex__Syms_H_
|
||||||
|
#define _VVortex__Syms_H_
|
||||||
|
|
||||||
|
#include "verilated.h"
|
||||||
|
|
||||||
|
// INCLUDE MODULE CLASSES
|
||||||
|
#include "VVortex.h"
|
||||||
|
#include "VVortex_VX_context_slave.h"
|
||||||
|
|
||||||
|
// SYMS CLASS
|
||||||
|
class VVortex__Syms : public VerilatedSyms {
|
||||||
|
public:
|
||||||
|
|
||||||
|
// LOCAL STATE
|
||||||
|
const char* __Vm_namep;
|
||||||
|
bool __Vm_didInit;
|
||||||
|
|
||||||
|
// SUBCELL STATE
|
||||||
|
VVortex* TOPp;
|
||||||
|
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one;
|
||||||
|
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one;
|
||||||
|
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one;
|
||||||
|
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one;
|
||||||
|
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one;
|
||||||
|
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one;
|
||||||
|
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one;
|
||||||
|
|
||||||
|
// CREATORS
|
||||||
|
VVortex__Syms(VVortex* topp, const char* namep);
|
||||||
|
~VVortex__Syms() {}
|
||||||
|
|
||||||
|
// METHODS
|
||||||
|
inline const char* name() { return __Vm_namep; }
|
||||||
|
|
||||||
|
} VL_ATTR_ALIGNED(64);
|
||||||
|
|
||||||
|
#endif // guard
|
||||||
1
rtl/obj_dir/VVortex__ver.d
Normal file
1
rtl/obj_dir/VVortex__ver.d
Normal file
@@ -0,0 +1 @@
|
|||||||
|
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_context_slave.cpp obj_dir/VVortex_VX_context_slave.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_context.v VX_context_slave.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_register_file_master_slave.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v
|
||||||
33
rtl/obj_dir/VVortex__verFiles.dat
Normal file
33
rtl/obj_dir/VVortex__verFiles.dat
Normal file
@@ -0,0 +1,33 @@
|
|||||||
|
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
|
||||||
|
C "-Wall -cc Vortex.v --exe test_bench.cpp"
|
||||||
|
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
|
||||||
|
S 2785 12891069980 1560309956 0 1560309956 0 "VX_alu.v"
|
||||||
|
S 3553 12891069981 1560309956 0 1560309956 0 "VX_context.v"
|
||||||
|
S 4995 12891069982 1560309956 0 1560309956 0 "VX_context_slave.v"
|
||||||
|
S 1699 12891069983 1560311423 0 1560311423 0 "VX_csr_handler.v"
|
||||||
|
S 5512 12891069984 1560309956 0 1560309956 0 "VX_d_e_reg.v"
|
||||||
|
S 17808 12891069985 1560309956 0 1560309956 0 "VX_decode.v"
|
||||||
|
S 1676 12891069987 1560310232 0 1560310232 0 "VX_define.v"
|
||||||
|
S 4267 12891069988 1560309956 0 1560309956 0 "VX_e_m_reg.v"
|
||||||
|
S 3692 12891069989 1560309956 0 1560309956 0 "VX_execute.v"
|
||||||
|
S 1751 12891069990 1560309956 0 1560309956 0 "VX_f_d_reg.v"
|
||||||
|
S 6204 12891069991 1560310568 0 1560310568 0 "VX_fetch.v"
|
||||||
|
S 6293 12891069992 1560309956 0 1560309956 0 "VX_forwarding.v"
|
||||||
|
S 1866 12891069993 1560309956 0 1560309956 0 "VX_m_w_reg.v"
|
||||||
|
S 4352 12891069994 1560310451 0 1560310451 0 "VX_memory.v"
|
||||||
|
S 1249 12891069995 1560309956 0 1560309956 0 "VX_register_file.v"
|
||||||
|
S 1655 12891069996 1560309956 0 1560309956 0 "VX_register_file_master_slave.v"
|
||||||
|
S 1599 12891069997 1560309956 0 1560309956 0 "VX_register_file_slave.v"
|
||||||
|
S 1915 12891069999 1560309956 0 1560309956 0 "VX_warp.v"
|
||||||
|
S 1568 12891070000 1560309956 0 1560309956 0 "VX_writeback.v"
|
||||||
|
S 18828 12891070001 1560309956 0 1560309956 0 "Vortex.v"
|
||||||
|
T 937577 12891114882 1560311425 0 1560311425 0 "obj_dir/VVortex.cpp"
|
||||||
|
T 33907 12891114881 1560311425 0 1560311425 0 "obj_dir/VVortex.h"
|
||||||
|
T 1800 12891114886 1560311425 0 1560311425 0 "obj_dir/VVortex.mk"
|
||||||
|
T 597541 12891114884 1560311425 0 1560311425 0 "obj_dir/VVortex_VX_context_slave.cpp"
|
||||||
|
T 19362 12891114883 1560311425 0 1560311425 0 "obj_dir/VVortex_VX_context_slave.h"
|
||||||
|
T 3668 12891114880 1560311425 0 1560311425 0 "obj_dir/VVortex__Syms.cpp"
|
||||||
|
T 1547 12891114879 1560311425 0 1560311425 0 "obj_dir/VVortex__Syms.h"
|
||||||
|
T 635 12891114889 1560311425 0 1560311425 0 "obj_dir/VVortex__ver.d"
|
||||||
|
T 0 0 1560311425 0 1560311425 0 "obj_dir/VVortex__verFiles.dat"
|
||||||
|
T 1187 12891114885 1560311425 0 1560311425 0 "obj_dir/VVortex_classes.mk"
|
||||||
39
rtl/obj_dir/VVortex_classes.mk
Normal file
39
rtl/obj_dir/VVortex_classes.mk
Normal file
@@ -0,0 +1,39 @@
|
|||||||
|
# Verilated -*- Makefile -*-
|
||||||
|
# DESCRIPTION: Verilator output: Make include file with class lists
|
||||||
|
#
|
||||||
|
# This file lists generated Verilated files, for including in higher level makefiles.
|
||||||
|
# See VVortex.mk for the caller.
|
||||||
|
|
||||||
|
### Switches...
|
||||||
|
# Coverage output mode? 0/1 (from --coverage)
|
||||||
|
VM_COVERAGE = 0
|
||||||
|
# Threaded output mode? 0/1/N threads (from --threads)
|
||||||
|
VM_THREADS = 0
|
||||||
|
# Tracing output mode? 0/1 (from --trace)
|
||||||
|
VM_TRACE = 0
|
||||||
|
|
||||||
|
### Object file lists...
|
||||||
|
# Generated module classes, fast-path, compile with highest optimization
|
||||||
|
VM_CLASSES_FAST += \
|
||||||
|
VVortex \
|
||||||
|
VVortex_VX_context_slave \
|
||||||
|
|
||||||
|
# Generated module classes, non-fast-path, compile with low/medium optimization
|
||||||
|
VM_CLASSES_SLOW += \
|
||||||
|
|
||||||
|
# Generated support classes, fast-path, compile with highest optimization
|
||||||
|
VM_SUPPORT_FAST += \
|
||||||
|
|
||||||
|
# Generated support classes, non-fast-path, compile with low/medium optimization
|
||||||
|
VM_SUPPORT_SLOW += \
|
||||||
|
VVortex__Syms \
|
||||||
|
|
||||||
|
# Global classes, need linked once per executable, fast-path, compile with highest optimization
|
||||||
|
VM_GLOBAL_FAST += \
|
||||||
|
verilated \
|
||||||
|
|
||||||
|
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
|
||||||
|
VM_GLOBAL_SLOW += \
|
||||||
|
|
||||||
|
|
||||||
|
# Verilated -*- Makefile -*-
|
||||||
4
rtl/obj_dir/test_bench.d
Normal file
4
rtl/obj_dir/test_bench.d
Normal file
@@ -0,0 +1,4 @@
|
|||||||
|
test_bench.o: ../test_bench.cpp ../test_bench.h ../VX_define.h ../ram.h \
|
||||||
|
VVortex.h \
|
||||||
|
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
|
||||||
|
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h
|
||||||
BIN
rtl/obj_dir/test_bench.o
Normal file
BIN
rtl/obj_dir/test_bench.o
Normal file
Binary file not shown.
9
rtl/obj_dir/verilated.d
Normal file
9
rtl/obj_dir/verilated.d
Normal file
@@ -0,0 +1,9 @@
|
|||||||
|
verilated.o: \
|
||||||
|
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.cpp \
|
||||||
|
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
|
||||||
|
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_imp.h \
|
||||||
|
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
|
||||||
|
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \
|
||||||
|
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_syms.h \
|
||||||
|
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_sym_props.h \
|
||||||
|
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_config.h
|
||||||
BIN
rtl/obj_dir/verilated.o
Normal file
BIN
rtl/obj_dir/verilated.o
Normal file
Binary file not shown.
@@ -4,7 +4,8 @@
|
|||||||
#define __RAM__
|
#define __RAM__
|
||||||
|
|
||||||
#include "string.h"
|
#include "string.h"
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <cstdint>
|
||||||
class RAM{
|
class RAM{
|
||||||
public:
|
public:
|
||||||
uint8_t* mem[1 << 12];
|
uint8_t* mem[1 << 12];
|
||||||
|
|||||||
@@ -0,0 +1,7 @@
|
|||||||
|
# Dynamic Instructions: 173969
|
||||||
|
# of total cycles: 175806
|
||||||
|
# of forwarding stalls: 0
|
||||||
|
# of branch stalls: 0
|
||||||
|
# CPI: 1.01056
|
||||||
|
# time to simulate: 6.95312e-310 milliseconds
|
||||||
|
# GRADE: Failed on test: 4294967295
|
||||||
|
|||||||
@@ -189,17 +189,17 @@ bool Vortex::dbus_driver()
|
|||||||
std::cerr << (char) data_write;
|
std::cerr << (char) data_write;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((addr >= 0x810002cc) && (addr < 0x810002d0))
|
// if ((addr >= 0x810002cc) && (addr < 0x810002d0))
|
||||||
{
|
// {
|
||||||
int index = (addr - 0x810002cc) / 4;
|
// int index = (addr - 0x810002cc) / 4;
|
||||||
std::cerr << GREEN << "1done[" << index << "] = " << data_write << DEFAULT << "\n";
|
// // std::cerr << GREEN << "1done[" << index << "] = " << data_write << DEFAULT << "\n";
|
||||||
}
|
// }
|
||||||
|
|
||||||
if ((addr >= 0x810059f4) && (addr < 0x810059f4))
|
// if ((addr >= 0x810059f4) && (addr < 0x810059f4))
|
||||||
{
|
// {
|
||||||
int index = (addr - 0x810059f4) / 4;
|
// int index = (addr - 0x810059f4) / 4;
|
||||||
std::cerr << RED << "2done[" << index << "] = " << data_write << DEFAULT << "\n";
|
// // std::cerr << RED << "2done[" << index << "] = " << data_write << DEFAULT << "\n";
|
||||||
}
|
// }
|
||||||
|
|
||||||
if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE)
|
if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE)
|
||||||
{
|
{
|
||||||
@@ -248,7 +248,7 @@ bool Vortex::dbus_driver()
|
|||||||
{
|
{
|
||||||
// printf("Reading mem - Addr: %x = %x\n", addr, data_read);
|
// printf("Reading mem - Addr: %x = %x\n", addr, data_read);
|
||||||
// std::cout << "READING - Addr: " << std::hex << addr << " = " << data_read << "\n";
|
// std::cout << "READING - Addr: " << std::hex << addr << " = " << data_read << "\n";
|
||||||
std::cout << std::dec;
|
// std::cout << std::dec;
|
||||||
vortex->in_cache_driver_out_data[curr_th] = data_read;
|
vortex->in_cache_driver_out_data[curr_th] = data_read;
|
||||||
|
|
||||||
} else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ)
|
} else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ)
|
||||||
|
|||||||
215904
rtl/worst_case_paths.rpt
Normal file
215904
rtl/worst_case_paths.rpt
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user