diff --git a/ci/blackbox.sh b/ci/blackbox.sh
index 12e93eb2..27b5f671 100755
--- a/ci/blackbox.sh
+++ b/ci/blackbox.sh
@@ -155,7 +155,7 @@ then
     
     if [ -f "$APP_PATH/trace.vcd" ]
     then 
-        mv $APP_PATH/trace.vcd .
+        mv -f $APP_PATH/trace.vcd .
     fi
 else
     if [ $SCOPE -eq 1 ]
diff --git a/driver/opae/vx_scope.cpp b/driver/opae/vx_scope.cpp
index 5cae4983..eb192250 100644
--- a/driver/opae/vx_scope.cpp
+++ b/driver/opae/vx_scope.cpp
@@ -140,7 +140,7 @@ int vx_scope_stop(fpga_handle hfpga) {
 
     std::cout << "scope trace dump begin..." << std::endl;
 
-    std::ofstream ofs("vx_scope.vcd");
+    std::ofstream ofs("trace.vcd");
 
     ofs << "$version Generated by Vortex Scope $end" << std::endl;
     ofs << "$timescale 1 ns $end" << std::endl;
diff --git a/hw/rtl/VX_csr_data.v b/hw/rtl/VX_csr_data.v
index 7217e77c..54bd1caf 100644
--- a/hw/rtl/VX_csr_data.v
+++ b/hw/rtl/VX_csr_data.v
@@ -40,8 +40,6 @@ module VX_csr_data #(
     
     reg [`NUM_WARPS-1:0][`FRM_BITS+`FFG_BITS-1:0] fcsr;
 
-    reg [31:0] read_data_r;
-
     always @(posedge clk) begin
 
         if (reset) begin
@@ -93,8 +91,12 @@ module VX_csr_data #(
         end
     end
 
+    reg [31:0] read_data_r;
+    reg read_addr_valid_r;
+
     always @(*) begin
         read_data_r = 'x;
+        read_addr_valid_r = 1;
         case (read_addr)
             `CSR_FFLAGS     : read_data_r = 32'(fcsr[read_wid][`FFG_BITS-1:0]);
             `CSR_FRM        : read_data_r = 32'(fcsr[read_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS]);
@@ -197,16 +199,19 @@ module VX_csr_data #(
             `CSR_MARCHID   : read_data_r = `ARCHITECTURE_ID;
             `CSR_MIMPID    : read_data_r = `IMPLEMENTATION_ID;
 
-            default: begin            
+            default: begin
                 if (!((read_addr >= `CSR_MPM_BASE && read_addr < (`CSR_MPM_BASE + 32))
                     | (read_addr >= `CSR_MPM_BASE_H && read_addr < (`CSR_MPM_BASE_H + 32)))) begin
-                    assert(~read_enable) else $error("%t: invalid CSR read address: %0h", $time, read_addr);
+                    read_addr_valid_r = 0;
                 end
             end
         endcase
     end 
 
+    `RUNTIME_ASSERT(~read_enable || read_addr_valid_r, ("invalid CSR read address: %0h", read_addr))
+
     assign read_data = read_data_r;
+    
     assign fpu_to_csr_if.read_frm = fcsr[fpu_to_csr_if.read_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS];
 
 endmodule
\ No newline at end of file