fill invalifator fix + refactoring

hw/opae/.gitignore

@@ -0,0 +1,2 @@
+build_ase*/
+build_fpga*/

hw/opae/Makefile

@@ -2,24 +2,32 @@
 ASE_BUILD_DIR=build_ase
 FPGA_BUILD_DIR=build_fpga
 
-all: ase fpga
+all: ase fpga fpga-1c
 
 ase: setup-ase
 	make -C $(ASE_BUILD_DIR)
 
-fpga: setup-fpga
-	cd $(FPGA_BUILD_DIR) && qsub-synth
-
 setup-ase: $(ASE_BUILD_DIR)/Makefile
 
-setup-fpga: $(FPGA_BUILD_DIR)/build/dcp.qpf
-
 $(ASE_BUILD_DIR)/Makefile:
 	afu_sim_setup -s sources.txt $(ASE_BUILD_DIR)
 
+fpga: setup-fpga
+	cd $(FPGA_BUILD_DIR) && qsub-synth
+
+setup-fpga: $(FPGA_BUILD_DIR)/build/dcp.qpf
+
 $(FPGA_BUILD_DIR)/build/dcp.qpf:
 	afu_synth_setup -s sources.txt $(FPGA_BUILD_DIR)
 
+fpga-1c: setup-fpga-1c
+	cd $(FPGA_BUILD_DIR)_1c && qsub-synth
+	
+setup-fpga-1c: $(FPGA_BUILD_DIR)_1c/build/dcp.qpf
+
+$(FPGA_BUILD_DIR)_1c/build/dcp.qpf:
+	afu_synth_setup -s sources_1c.txt $(FPGA_BUILD_DIR)_1c
+
 run-ase:
 	cd $(ASE_BUILD_DIR) && make sim
 

hw/opae/sources.txt

@@ -4,19 +4,6 @@ vortex_afu.json
 
 +define+NUM_CORES=2
 
-+define+DPRFQ_SIZE=0 
-+define+IPRFQ_SIZE=0 
-+define+SPRFQ_SIZE=0 
-+define+L2PRFQ_SIZE=0 
-+define+L3PRFQ_SIZE=0
-
-+define+DFILL_INVALIDAOR_SIZE=0 
-+define+IFILL_INVALIDAOR_SIZE=0 
-+define+SFILL_INVALIDAOR_SIZE=0 
-+define+L2FILL_INVALIDAOR_SIZE=0 
-+define+L3FILL_INVALIDAOR_SIZE=0
-
-
 #+define+DBG_PRINT_CORE_ICACHE
 #+define+DBG_PRINT_CORE_DCACHE
 #+define+DBG_PRINT_CACHE_BANK