minor ibuffer critical path optimization.
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8
hw/rtl/cache/VX_bank.v
vendored
8
hw/rtl/cache/VX_bank.v
vendored
@@ -558,11 +558,11 @@ module VX_bank #(
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`ifdef DBG_PRINT_CACHE_BANK
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always @(posedge clk) begin
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/*if (valid_st1 && pmask_st1 == {NUM_PORTS{1'b1}}) begin
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$display("%t: cache%0d:%0d full bank multi-porting - addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
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end*/
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/*if (crsq_in_fire && (NUM_PORTS > 1) && $countones(crsq_pmask) > 1) begin
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$display("%t: *** cache%0d:%0d multi-port-out: pmask=%b, addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, crsq_pmask, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), crsq_tag);
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end */
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if (valid_st1 && !is_fill_st1 && miss_st1 && incoming_fill_qual_st1) begin
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$display("%t: cache%0d:%0d miss with incoming fill - addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
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$display("%t: *** cache%0d:%0d miss with incoming fill - addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
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assert(!is_mshr_st1);
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end
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if (crsq_in_stall || dreq_alm_full || mshr_alm_full) begin
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