minor ibuffer critical path optimization.
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@@ -31,7 +31,7 @@ module VX_scoreboard #(
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if (release_reg) begin
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inuse_regs[writeback_if.wid][writeback_if.rd] <= 0;
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assert(inuse_regs[writeback_if.wid][writeback_if.rd] != 0)
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else $error("*** %t: core%0d: invalid writeback register: wid=%0d, PC=%0h, rd=%0d",
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else $error("%t: *** core%0d: invalid writeback register: wid=%0d, PC=%0h, rd=%0d",
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$time, CORE_ID, writeback_if.wid, writeback_if.PC, writeback_if.rd);
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end
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end
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@@ -40,7 +40,7 @@ module VX_scoreboard #(
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if (ibuf_deq_if.valid && ~ibuf_deq_if.ready) begin
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$display("%t: core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
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$display("%t: *** core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
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$time, CORE_ID, ibuf_deq_if.wid, ibuf_deq_if.PC, ibuf_deq_if.rd, ibuf_deq_if.wb,
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deq_inuse_regs[ibuf_deq_if.rd], deq_inuse_regs[ibuf_deq_if.rs1], deq_inuse_regs[ibuf_deq_if.rs2], deq_inuse_regs[ibuf_deq_if.rs3]);
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end
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@@ -54,7 +54,7 @@ module VX_scoreboard #(
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deadlock_ctr <= 0;
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end else if (ibuf_deq_if.valid && ~ibuf_deq_if.ready) begin
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deadlock_ctr <= deadlock_ctr + 1;
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assert(deadlock_ctr < deadlock_timeout) else $error("*** %t: core%0d-deadlock: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
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assert(deadlock_ctr < deadlock_timeout) else $error("%t: *** core%0d-deadlock: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
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$time, CORE_ID, ibuf_deq_if.wid, ibuf_deq_if.PC, ibuf_deq_if.rd, ibuf_deq_if.wb,
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deq_inuse_regs[ibuf_deq_if.rd], deq_inuse_regs[ibuf_deq_if.rs1], deq_inuse_regs[ibuf_deq_if.rs2], deq_inuse_regs[ibuf_deq_if.rs3]);
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end else if (ibuf_deq_if.valid && ibuf_deq_if.ready) begin
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