From af1cecae07a430cb54780a7e7e97dd57bca62269 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 6 Sep 2021 23:38:20 -0700 Subject: [PATCH] stream arbiter update --- hw/rtl/VX_cluster.v | 15 ++++++++------- hw/rtl/VX_mem_arb.v | 2 +- hw/rtl/VX_mem_unit.v | 3 ++- hw/rtl/VX_smem_arb.v | 2 +- hw/rtl/Vortex.v | 13 +++++++------ hw/rtl/afu/VX_avs_wrapper.v | 1 + hw/rtl/afu/vortex_afu.sv | 4 ++-- hw/rtl/cache/VX_cache.v | 3 ++- hw/rtl/libs/VX_stream_arbiter.v | 4 ++-- 9 files changed, 26 insertions(+), 21 deletions(-) diff --git a/hw/rtl/VX_cluster.v b/hw/rtl/VX_cluster.v index 04719719..35b933bb 100644 --- a/hw/rtl/VX_cluster.v +++ b/hw/rtl/VX_cluster.v @@ -147,13 +147,14 @@ module VX_cluster #( `RESET_RELAY (mem_arb_reset); VX_mem_arb #( - .NUM_REQS (`NUM_CORES), - .DATA_WIDTH (`DMEM_DATA_WIDTH), - .ADDR_WIDTH (`DMEM_ADDR_WIDTH), - .TAG_IN_WIDTH (`XMEM_TAG_WIDTH), - .TAG_SEL_IDX (1), // Skip 0 for NC flag - .BUFFERED_REQ (1), - .BUFFERED_RSP (1) + .NUM_REQS (`NUM_CORES), + .DATA_WIDTH (`DMEM_DATA_WIDTH), + .ADDR_WIDTH (`DMEM_ADDR_WIDTH), + .TAG_IN_WIDTH (`XMEM_TAG_WIDTH), + .TYPE ("R"), + .TAG_SEL_IDX (1), // Skip 0 for NC flag + .BUFFERED_REQ (1), + .BUFFERED_RSP (1) ) mem_arb ( .clk (clk), .reset (mem_arb_reset), diff --git a/hw/rtl/VX_mem_arb.v b/hw/rtl/VX_mem_arb.v index 2864684e..a1f27f81 100644 --- a/hw/rtl/VX_mem_arb.v +++ b/hw/rtl/VX_mem_arb.v @@ -8,7 +8,7 @@ module VX_mem_arb #( parameter TAG_SEL_IDX = 0, parameter BUFFERED_REQ = 0, parameter BUFFERED_RSP = 0, - parameter TYPE = "R", + parameter TYPE = "P", localparam DATA_SIZE = (DATA_WIDTH / 8), localparam LOG_NUM_REQS = `CLOG2(NUM_REQS), diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.v index 98a50892..a889216e 100644 --- a/hw/rtl/VX_mem_unit.v +++ b/hw/rtl/VX_mem_unit.v @@ -206,7 +206,7 @@ module VX_mem_unit # ( .LANES (`NUM_THREADS), .DATA_SIZE (4), .TAG_IN_WIDTH (`DCORE_TAG_WIDTH), - .TYPE ("X"), + .TYPE ("P"), .BUFFERED_REQ (2), .BUFFERED_RSP (1) ) smem_arb ( @@ -316,6 +316,7 @@ module VX_mem_unit # ( .DATA_WIDTH (`DMEM_DATA_WIDTH), .ADDR_WIDTH (`DMEM_ADDR_WIDTH), .TAG_IN_WIDTH (`DMEM_TAG_WIDTH), + .TYPE ("R"), .TAG_SEL_IDX (1), // Skip 0 for NC flag .BUFFERED_REQ (1), .BUFFERED_RSP (2) diff --git a/hw/rtl/VX_smem_arb.v b/hw/rtl/VX_smem_arb.v index 45033f5c..07b13730 100644 --- a/hw/rtl/VX_smem_arb.v +++ b/hw/rtl/VX_smem_arb.v @@ -8,7 +8,7 @@ module VX_smem_arb #( parameter TAG_SEL_IDX = 0, parameter BUFFERED_REQ = 0, parameter BUFFERED_RSP = 0, - parameter TYPE = "R", + parameter TYPE = "P", localparam ADDR_WIDTH = (32-`CLOG2(DATA_SIZE)), localparam DATA_WIDTH = (8 * DATA_SIZE), diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index f1be995d..ab55c968 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -145,12 +145,13 @@ module Vortex ( `RESET_RELAY (mem_arb_reset); VX_mem_arb #( - .NUM_REQS (`NUM_CLUSTERS), - .DATA_WIDTH (`L3MEM_DATA_WIDTH), - .ADDR_WIDTH (`L3MEM_ADDR_WIDTH), - .TAG_IN_WIDTH (`L2MEM_TAG_WIDTH), - .BUFFERED_REQ (1), - .BUFFERED_RSP (1) + .NUM_REQS (`NUM_CLUSTERS), + .DATA_WIDTH (`L3MEM_DATA_WIDTH), + .ADDR_WIDTH (`L3MEM_ADDR_WIDTH), + .TAG_IN_WIDTH (`L2MEM_TAG_WIDTH), + .TYPE ("R"), + .BUFFERED_REQ (1), + .BUFFERED_RSP (1) ) mem_arb ( .clk (clk), .reset (mem_arb_reset), diff --git a/hw/rtl/afu/VX_avs_wrapper.v b/hw/rtl/afu/VX_avs_wrapper.v index f6c3e8fd..6901870a 100644 --- a/hw/rtl/afu/VX_avs_wrapper.v +++ b/hw/rtl/afu/VX_avs_wrapper.v @@ -149,6 +149,7 @@ module VX_avs_wrapper #( VX_stream_arbiter #( .NUM_REQS (AVS_BANKS), .DATAW (AVS_DATA_WIDTH + REQ_TAG_WIDTH), + .TYPE ("R"), .BUFFERED (OUTPUT_REG ? 1 : 0) ) rsp_arb ( .clk (clk), diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv index 70208392..5efe0b2e 100644 --- a/hw/rtl/afu/vortex_afu.sv +++ b/hw/rtl/afu/vortex_afu.sv @@ -519,9 +519,9 @@ VX_mem_arb #( .DATA_WIDTH (LMEM_DATA_WIDTH), .ADDR_WIDTH (LMEM_ADDR_WIDTH), .TAG_IN_WIDTH (AVS_REQ_TAGW), + .TYPE ("P"), .BUFFERED_REQ (0), - .BUFFERED_RSP (0), - .TYPE ("X") + .BUFFERED_RSP (0) ) mem_arb ( .clk (clk), .reset (mem_arb_reset), diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index a50164a0..b8644b1e 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -617,7 +617,8 @@ module VX_cache #( VX_stream_arbiter #( .NUM_REQS (NUM_BANKS), .DATAW (`MEM_ADDR_WIDTH + MSHR_ADDR_WIDTH + 1 + NUM_PORTS * (1 + WORD_SIZE + WORD_SELECT_BITS + `WORD_WIDTH)), - .BUFFERED (1) + .BUFFERED (1), + .TYPE ("R") ) mem_req_arb ( .clk (clk), .reset (mreq_reset), diff --git a/hw/rtl/libs/VX_stream_arbiter.v b/hw/rtl/libs/VX_stream_arbiter.v index b8da4f3f..c97798c8 100644 --- a/hw/rtl/libs/VX_stream_arbiter.v +++ b/hw/rtl/libs/VX_stream_arbiter.v @@ -4,7 +4,7 @@ module VX_stream_arbiter #( parameter NUM_REQS = 1, parameter LANES = 1, parameter DATAW = 1, - parameter TYPE = "R", + parameter TYPE = "P", parameter LOCK_ENABLE = 1, parameter BUFFERED = 0 ) ( @@ -41,7 +41,7 @@ module VX_stream_arbiter #( assign sel_ready = ready_in_sel; end - if (TYPE == "X") begin + if (TYPE == "P") begin `UNUSED_VAR (sel_ready) VX_lzc #( .N (NUM_REQS)