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non-cacheable memory address critical paths optimizations

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Blaise Tine
2021-06-10 12:47:18 -07:00
parent 41069ba188
commit adf033b0aa
11 changed files with 258 additions and 194 deletions
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66
hw/rtl/VX_smem_arb.v
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@@ -18,7 +18,7 @@ module VX_smem_arb (
// output response
VX_dcache_core_rsp_if core_rsp_if
);
localparam REQ_DATAW = 1 + `DCORE_ADDR_WIDTH + 1 + `DWORD_SIZE + (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH - 1;
localparam REQ_DATAW = `DCORE_ADDR_WIDTH + 1 + `DWORD_SIZE + (`DWORD_SIZE*8) + (`DCORE_TAG_WIDTH-1);
localparam RSP_DATAW = `NUM_THREADS + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH;
//
@@ -26,71 +26,59 @@ module VX_smem_arb (
//
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
wire cache_req_valid_out;
wire cache_req_ready_out;
wire is_smem_addr_out;
wire is_smem_addr_in = core_req_if.tag[i][0];
VX_skid_buffer #(
.DATAW (REQ_DATAW)
) out_buffer (
wire [1:0][REQ_DATAW-1:0] req_data_out;
VX_stream_demux #(
.NUM_REQS (2),
.DATAW (REQ_DATAW),
.BUFFERED (0)
) rsp_demux (
.clk (clk),
.reset (reset),
.valid_in (core_req_if.valid[i]),
.data_in ({is_smem_addr_in, core_req_if.addr[i], core_req_if.rw[i], core_req_if.byteen[i], core_req_if.data[i], core_req_if.tag[i][`DCORE_TAG_WIDTH-1:1]}),
.ready_in (core_req_if.ready[i]),
.valid_out (cache_req_valid_out),
.data_out ({is_smem_addr_out, cache_req_if.addr[i], cache_req_if.rw[i], cache_req_if.byteen[i], cache_req_if.data[i], cache_req_if.tag[i]}),
.ready_out (cache_req_ready_out)
);
.sel (core_req_if.tag[i][0]),
.valid_in (core_req_if.valid[i]),
.data_in ({core_req_if.addr[i], core_req_if.rw[i], core_req_if.byteen[i], core_req_if.data[i], core_req_if.tag[i][`DCORE_TAG_WIDTH-1:1]}),
.ready_in (core_req_if.ready[i]),
.valid_out ({smem_req_if.valid[i], cache_req_if.valid[i]}),
.data_out (req_data_out),
.ready_out ({smem_req_if.ready[i], cache_req_if.ready[i]})
);
assign cache_req_if.valid[i] = cache_req_valid_out && ~is_smem_addr_out;
assign smem_req_if.valid[i] = cache_req_valid_out && is_smem_addr_out;
assign cache_req_ready_out = is_smem_addr_out ? smem_req_if.ready[i] : cache_req_if.ready[i];
assign smem_req_if.addr[i] = cache_req_if.addr[i];
assign smem_req_if.rw[i] = cache_req_if.rw[i];
assign smem_req_if.byteen[i] = cache_req_if.byteen[i];
assign smem_req_if.data[i] = cache_req_if.data[i];
assign smem_req_if.tag[i] = cache_req_if.tag[i];
assign {cache_req_if.addr[i], cache_req_if.rw[i], cache_req_if.byteen[i], cache_req_if.data[i], cache_req_if.tag[i]} = req_data_out[0];
assign {smem_req_if.addr[i], smem_req_if.rw[i], smem_req_if.byteen[i], smem_req_if.data[i], smem_req_if.tag[i]} = req_data_out[1];
end
//
// handle responses
//
wire [1:0][RSP_DATAW-1:0] rsp_data_in;
wire [1:0] rsp_valid_in;
wire [1:0] rsp_ready_in;
wire [1:0][RSP_DATAW-1:0] rsp_data_in;
wire [`NUM_THREADS-1:0] core_rsp_tmask;
wire core_rsp_valid;
wire [`NUM_THREADS-1:0] core_rsp_valid_tmask;
assign rsp_valid_in[0] = (| cache_rsp_if.valid);
assign rsp_valid_in[1] = (| smem_rsp_if.valid);
assign rsp_data_in[0] = {cache_rsp_if.valid, cache_rsp_if.data, {cache_rsp_if.tag, 1'b0}};
assign rsp_data_in[1] = {smem_rsp_if.valid, smem_rsp_if.data, {smem_rsp_if.tag, 1'b1}};
assign rsp_valid_in[0] = (| cache_rsp_if.valid);
assign rsp_valid_in[1] = (| smem_rsp_if.valid) & `SM_ENABLE;
VX_stream_arbiter #(
.NUM_REQS (2),
.DATAW (RSP_DATAW),
.DATAW (RSP_DATAW),
.BUFFERED (1)
) rsp_arb (
.clk (clk),
.reset (reset),
.valid_in (rsp_valid_in),
.data_in (rsp_data_in),
.ready_in (rsp_ready_in),
.ready_in ({smem_rsp_if.ready, cache_rsp_if.ready}),
.valid_out (core_rsp_valid),
.data_out ({core_rsp_valid_tmask, core_rsp_if.data, core_rsp_if.tag}),
.data_out ({core_rsp_tmask, core_rsp_if.data, core_rsp_if.tag}),
.ready_out (core_rsp_if.ready)
);
assign cache_rsp_if.ready = rsp_ready_in[0];
assign smem_rsp_if.ready = rsp_ready_in[1];
assign core_rsp_if.valid = {`NUM_THREADS{core_rsp_valid}} & core_rsp_valid_tmask;
assign core_rsp_if.valid = {`NUM_THREADS{core_rsp_valid}} & core_rsp_tmask;
endmodule