From acafcceb9453a0a454b65d833b021cf8f0456467 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 26 Mar 2020 03:56:44 -0400 Subject: [PATCH] fixed Modelsim build errors --- rtl/VX_alu.v | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/rtl/VX_alu.v b/rtl/VX_alu.v index 53b05b2d..07b090e6 100644 --- a/rtl/VX_alu.v +++ b/rtl/VX_alu.v @@ -25,6 +25,9 @@ module VX_alu( wire[63:0] mul_data_a, mul_data_b; wire[63:0] mul_result; + wire[31:0] ALU_in1; + wire[31:0] ALU_in2; + VX_divide #( .WIDTHN(32), .WIDTHD(32), @@ -123,9 +126,6 @@ module VX_alu( `ifdef SYN_FUNC wire which_in2; - - wire[31:0] ALU_in1; - wire[31:0] ALU_in2; wire[31:0] upper_immed; assign which_in2 = in_rs2_src == `RS2_IMMED; @@ -164,10 +164,7 @@ module VX_alu( end `else - wire which_in2; - - wire[31:0] ALU_in1; - wire[31:0] ALU_in2; + wire which_in2; wire[31:0] upper_immed; @@ -209,4 +206,4 @@ module VX_alu( end `endif -endmodule : VX_alu +endmodule : VX_alu \ No newline at end of file