Before FE BE abstraction
This commit is contained in:
felsabbagh3
169
rtl/pipe_regs/VX_d_e_reg.v
Normal file
169
rtl/pipe_regs/VX_d_e_reg.v
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`include "VX_define.v"
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module VX_d_e_reg (
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input wire clk,
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input wire reset,
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input wire in_fwd_stall,
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input wire in_branch_stall,
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input wire in_freeze,
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input wire in_clone_stall,
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VX_frE_to_bckE_req_inter VX_frE_to_bckE_req,
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VX_frE_to_bckE_req_inter VX_bckE_req
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);
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wire stall = in_freeze;
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wire flush = (in_fwd_stall == `STALL) || (in_branch_stall == `STALL) || (in_clone_stall == `STALL);
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VX_generic_register #(.N(490)) d_e_reg
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(
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.clk (clk),
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.reset(reset),
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.stall(stall),
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.flush(flush),
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.in ({VX_frE_to_bckE_req.csr_address, VX_frE_to_bckE_req.is_csr, VX_frE_to_bckE_req.csr_mask, VX_frE_to_bckE_req.rd, VX_frE_to_bckE_req.rs1, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.a_reg_data, VX_frE_to_bckE_req.b_reg_data, VX_frE_to_bckE_req.alu_op, VX_frE_to_bckE_req.wb, VX_frE_to_bckE_req.rs2_src, VX_frE_to_bckE_req.itype_immed, VX_frE_to_bckE_req.mem_read, VX_frE_to_bckE_req.mem_write, VX_frE_to_bckE_req.branch_type, VX_frE_to_bckE_req.upper_immed, VX_frE_to_bckE_req.curr_PC, VX_frE_to_bckE_req.jal, VX_frE_to_bckE_req.jal_offset, VX_frE_to_bckE_req.PC_next, VX_frE_to_bckE_req.valid, VX_frE_to_bckE_req.warp_num}),
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.out ({VX_bckE_req.csr_address , VX_bckE_req.is_csr , VX_bckE_req.csr_mask , VX_bckE_req.rd , VX_bckE_req.rs1 , VX_bckE_req.rs2 , VX_bckE_req.a_reg_data , VX_bckE_req.b_reg_data , VX_bckE_req.alu_op , VX_bckE_req.wb , VX_bckE_req.rs2_src , VX_bckE_req.itype_immed , VX_bckE_req.mem_read , VX_bckE_req.mem_write , VX_bckE_req.branch_type , VX_bckE_req.upper_immed , VX_bckE_req.curr_PC , VX_bckE_req.jal , VX_bckE_req.jal_offset , VX_bckE_req.PC_next , VX_bckE_req.valid , VX_bckE_req.warp_num})
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);
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// wire[`NT_M1:0][31:0] temp_out_a_reg_data;
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// wire[`NT_M1:0][31:0] temp_out_b_reg_data;
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// wire[`NT_M1:0] temp_out_valid;
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// genvar index;
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// for (index = 0; index <= `NT_M1; index = index + 1) begin
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// assign out_valid[index] = temp_out_valid[index];
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// assign out_a_reg_data[index] = temp_out_a_reg_data[index];
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// assign out_b_reg_data[index] = temp_out_b_reg_data[index];
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// end
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// reg[4:0] rd;
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// reg[4:0] rs1;
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// reg[4:0] rs2;
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// reg[31:0] a_reg_data[`NT_M1:0];
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// reg[31:0] b_reg_data[`NT_M1:0];
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// reg[4:0] alu_op;
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// reg[1:0] wb;
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// reg[31:0] PC_next_out;
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// reg rs2_src;
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// reg[31:0] itype_immed;
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// reg[2:0] mem_read;
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// reg[2:0] mem_write;
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// reg[2:0] branch_type;
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// reg[19:0] upper_immed;
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// reg[11:0] csr_address;
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// reg is_csr;
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// reg[31:0] csr_mask;
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// reg[31:0] curr_PC;
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// reg jal;
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// reg[31:0] jal_offset;
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// reg valid[`NT_M1:0];
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// reg[31:0] reg_data_z[`NT_M1:0];
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// reg valid_z[`NT_M1:0];
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// reg[`NW_M1:0] warp_num;
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// integer ini_reg;
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// initial begin
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// rd = 0;
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// rs1 = 0;
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// for (ini_reg = 0; ini_reg < `NT; ini_reg = ini_reg + 1)
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// begin
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// a_reg_data[ini_reg] = 0;
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// b_reg_data[ini_reg] = 0;
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// reg_data_z[ini_reg] = 0;
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// valid[ini_reg] = 0;
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// valid_z[ini_reg] = 0;
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// end
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// rs2 = 0;
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// alu_op = 0;
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// wb = `NO_WB;
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// PC_next_out = 0;
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// rs2_src = 0;
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// itype_immed = 0;
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// mem_read = `NO_MEM_READ;
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// mem_write = `NO_MEM_WRITE;
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// branch_type = `NO_BRANCH;
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// upper_immed = 0;
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// csr_address = 0;
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// is_csr = 0;
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// csr_mask = 0;
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// curr_PC = 0;
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// jal = `NO_JUMP;
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// jal_offset = 0;
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// warp_num = 0;
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// end
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// wire stalling;
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// assign stalling = (in_fwd_stall == `STALL) || (in_branch_stall == `STALL) || (in_clone_stall == `STALL);
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// Freeze stall
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// Stalling flush
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// assign out_rd = rd;
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// assign out_rs1 = rs1;
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// assign out_rs2 = rs2;
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// assign out_a_reg_data = a_reg_data;
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// assign out_b_reg_data = b_reg_data;
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// assign out_alu_op = alu_op;
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// assign out_wb = wb;
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// assign out_PC_next = PC_next_out;
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// assign out_rs2_src = rs2_src;
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// assign out_itype_immed = itype_immed;
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// assign out_mem_read = mem_read;
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// assign out_mem_write = mem_write;
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// assign out_branch_type = branch_type;
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// assign out_upper_immed = upper_immed;
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// assign out_csr_address = csr_address;
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// assign out_is_csr = is_csr;
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// assign out_csr_mask = csr_mask;
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// assign out_jal = jal;
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// assign out_jal_offset = jal_offset;
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// assign out_curr_PC = curr_PC;
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// assign out_valid = valid;
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// assign out_warp_num = warp_num;
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// always @(posedge clk) begin
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// if (in_freeze == 1'h0) begin
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// rd <= stalling ? 5'h0 : in_rd;
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// rs1 <= stalling ? 5'h0 : in_rs1;
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// rs2 <= stalling ? 5'h0 : in_rs2;
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// a_reg_data <= stalling ? reg_data_z : in_a_reg_data;
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// b_reg_data <= stalling ? reg_data_z : in_b_reg_data;
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// alu_op <= stalling ? `NO_ALU : in_alu_op;
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// wb <= stalling ? `NO_WB : in_wb;
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// PC_next_out <= stalling ? 32'h0 : in_PC_next;
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// rs2_src <= stalling ? `RS2_REG : in_rs2_src;
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// itype_immed <= stalling ? 32'hdeadbeef : in_itype_immed;
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// mem_read <= stalling ? `NO_MEM_READ : in_mem_read;
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// mem_write <= stalling ? `NO_MEM_WRITE: in_mem_write;
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// branch_type <= stalling ? `NO_BRANCH : in_branch_type;
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// upper_immed <= stalling ? 20'h0 : in_upper_immed;
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// csr_address <= stalling ? 12'h0 : in_csr_address;
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// is_csr <= stalling ? 1'h0 : in_is_csr;
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// csr_mask <= stalling ? 32'h0 : in_csr_mask;
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// jal <= stalling ? `NO_JUMP : in_jal;
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// jal_offset <= stalling ? 32'h0 : in_jal_offset;
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// curr_PC <= stalling ? 32'h0 : in_curr_PC;
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// valid <= stalling ? valid_z : in_valid;
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// warp_num <= stalling ? 0 : in_warp_num;
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// end
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// end
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endmodule
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45
rtl/pipe_regs/VX_e_m_reg.v
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45
rtl/pipe_regs/VX_e_m_reg.v
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`include "VX_define.v"
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module VX_e_m_reg (
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input wire clk,
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input wire reset,
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input wire in_freeze,
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input wire[11:0] in_csr_address,
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input wire in_is_csr,
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input wire[31:0] in_csr_result,
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input wire in_jal,
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input wire[31:0] in_jal_dest,
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VX_mem_req_inter VX_exe_mem_req,
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VX_mem_req_inter VX_mem_req,
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output wire[11:0] out_csr_address,
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output wire out_is_csr,
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output wire[31:0] out_csr_result,
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output wire out_jal,
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output wire[31:0] out_jal_dest
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);
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wire flush = 0;
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wire stall = in_freeze;
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VX_generic_register #(.N(464)) f_d_reg
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(
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.clk (clk),
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.reset(reset),
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.stall(stall),
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.flush(flush),
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.in ({in_csr_address , in_is_csr , in_csr_result , in_jal , in_jal_dest , VX_exe_mem_req.alu_result, VX_exe_mem_req.mem_read, VX_exe_mem_req.mem_write, VX_exe_mem_req.rd, VX_exe_mem_req.wb, VX_exe_mem_req.rs1, VX_exe_mem_req.rs2, VX_exe_mem_req.rd2, VX_exe_mem_req.PC_next, VX_exe_mem_req.curr_PC, VX_exe_mem_req.branch_offset, VX_exe_mem_req.branch_type, VX_exe_mem_req.valid, VX_exe_mem_req.warp_num}),
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.out ({out_csr_address, out_is_csr, out_csr_result, out_jal, out_jal_dest, VX_mem_req.alu_result , VX_mem_req.mem_read , VX_mem_req.mem_write , VX_mem_req.rd , VX_mem_req.wb , VX_mem_req.rs1 , VX_mem_req.rs2 , VX_mem_req.rd2 , VX_mem_req.PC_next , VX_mem_req.curr_PC , VX_mem_req.branch_offset , VX_mem_req.branch_type , VX_mem_req.valid , VX_mem_req.warp_num})
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);
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endmodule // VX_e_m_reg
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33
rtl/pipe_regs/VX_f_d_reg.v
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33
rtl/pipe_regs/VX_f_d_reg.v
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@@ -0,0 +1,33 @@
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`include "buses.vh"
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`include "VX_define.v"
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module VX_f_d_reg (
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input wire clk,
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input wire reset,
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input wire in_fwd_stall,
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input wire in_freeze,
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input wire in_clone_stall,
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VX_inst_meta_inter fe_inst_meta_fd,
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VX_inst_meta_inter fd_inst_meta_de
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);
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wire flush = 1'b0;
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wire stall = in_fwd_stall == 1'b1 || in_freeze == 1'b1 || in_clone_stall;
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VX_generic_register #(.N(72)) f_d_reg
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(
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.clk (clk),
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.reset(reset),
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.stall(stall),
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.flush(flush),
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.in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.inst_pc, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}),
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.out ({fd_inst_meta_de.instruction, fd_inst_meta_de.inst_pc, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid})
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);
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endmodule
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33
rtl/pipe_regs/VX_m_w_reg.v
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33
rtl/pipe_regs/VX_m_w_reg.v
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@@ -0,0 +1,33 @@
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`include "VX_define.v"
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module VX_m_w_reg (
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input wire clk,
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input wire reset,
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input wire in_freeze,
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VX_inst_mem_wb_inter VX_mem_wb,
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VX_mw_wb_inter VX_mw_wb
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);
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wire flush = 0;
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wire stall = in_freeze;
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VX_generic_register #(.N(303)) m_w_reg
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(
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.clk (clk),
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.reset(reset),
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.stall(stall),
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.flush(flush),
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.in ({VX_mem_wb.alu_result, VX_mem_wb.mem_result, VX_mem_wb.rd, VX_mem_wb.wb, VX_mem_wb.PC_next, VX_mem_wb.valid, VX_mem_wb.warp_num}),
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.out ({VX_mw_wb.alu_result , VX_mw_wb.mem_result , VX_mw_wb.rd , VX_mw_wb.wb , VX_mw_wb.PC_next , VX_mw_wb.valid , VX_mw_wb.warp_num })
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);
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endmodule // VX_m_w_reg
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