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Before FE BE abstraction

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This commit is contained in:
felsabbagh3
2019-09-08 16:21:37 -04:00
parent fe09aafbb4
commit ac9b06bf7d
49 changed files with 6237 additions and 5268 deletions
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101
rtl/VX_forwarding.v
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@@ -3,51 +3,54 @@
module VX_forwarding (
// INFO FROM DECODE
input wire[4:0] in_decode_src1,
input wire[4:0] in_decode_src2,
input wire[11:0] in_decode_csr_address,
input wire[`NW_M1:0] in_decode_warp_num,
VX_forward_reqeust_inter VX_fwd_req_de,
VX_forward_exe_inter VX_fwd_exe,
VX_forward_mem_inter VX_fwd_mem,
VX_forward_wb_inter VX_fwd_wb,
// INFO FROM EXE
input wire[4:0] in_execute_dest,
input wire[1:0] in_execute_wb,
input wire[`NT_M1:0][31:0] in_execute_alu_result,
input wire[31:0] in_execute_PC_next,
input wire in_execute_is_csr,
input wire[11:0] in_execute_csr_address,
input wire[`NW_M1:0] in_execute_warp_num,
// INFO FROM MEM
input wire[4:0] in_memory_dest,
input wire[1:0] in_memory_wb,
input wire[`NT_M1:0][31:0] in_memory_alu_result,
input wire[`NT_M1:0][31:0] in_memory_mem_data,
input wire[31:0] in_memory_PC_next,
input wire in_memory_is_csr,
input wire[11:0] in_memory_csr_address,
input wire[31:0] in_memory_csr_result,
input wire[`NW_M1:0] in_memory_warp_num,
// INFO FROM WB
input wire[4:0] in_writeback_dest,
input wire[1:0] in_writeback_wb,
input wire[`NT_M1:0][31:0] in_writeback_alu_result,
input wire[`NT_M1:0][31:0] in_writeback_mem_data,
input wire[31:0] in_writeback_PC_next,
input wire[`NW_M1:0] in_writeback_warp_num,
// OUT SIGNALS
output wire out_src1_fwd,
output wire out_src2_fwd,
output wire out_csr_fwd,
output wire[`NT_M1:0][31:0] out_src1_fwd_data,
output wire[`NT_M1:0][31:0] out_src2_fwd_data,
output wire[31:0] out_csr_fwd_data,
output wire out_fwd_stall
VX_forward_response_inter VX_fwd_rsp,
output wire out_fwd_stall
);
wire[4:0] in_decode_src1 = VX_fwd_req_de.src1;
wire[4:0] in_decode_src2 = VX_fwd_req_de.src2;
wire[`NW_M1:0] in_decode_warp_num = VX_fwd_req_de.warp_num;
wire[4:0] in_execute_dest = VX_fwd_exe.dest;
wire[1:0] in_execute_wb = VX_fwd_exe.wb;
wire[`NT_M1:0][31:0] in_execute_alu_result = VX_fwd_exe.alu_result;
wire[31:0] in_execute_PC_next = VX_fwd_exe.PC_next;
wire[`NW_M1:0] in_execute_warp_num = VX_fwd_exe.warp_num;
wire[4:0] in_memory_dest = VX_fwd_mem.dest;
wire[1:0] in_memory_wb = VX_fwd_mem.wb;
wire[`NT_M1:0][31:0] in_memory_alu_result = VX_fwd_mem.alu_result;
wire[`NT_M1:0][31:0] in_memory_mem_data = VX_fwd_mem.mem_data;
wire[31:0] in_memory_PC_next = VX_fwd_mem.PC_next;
wire[`NW_M1:0] in_memory_warp_num = VX_fwd_mem.warp_num;
wire[4:0] in_writeback_dest = VX_fwd_wb.dest;
wire[1:0] in_writeback_wb = VX_fwd_wb.wb;
wire[`NT_M1:0][31:0] in_writeback_alu_result = VX_fwd_wb.alu_result;
wire[`NT_M1:0][31:0] in_writeback_mem_data = VX_fwd_wb.mem_data;
wire[31:0] in_writeback_PC_next = VX_fwd_wb.PC_next;
wire[`NW_M1:0] in_writeback_warp_num = VX_fwd_wb.warp_num;
wire out_src1_fwd;
wire out_src2_fwd;
wire[`NT_M1:0][31:0] out_src1_fwd_data;
wire[`NT_M1:0][31:0] out_src2_fwd_data;
assign VX_fwd_rsp.src1_fwd = out_src1_fwd;
assign VX_fwd_rsp.src2_fwd = out_src2_fwd;
assign VX_fwd_rsp.src1_fwd_data = out_src1_fwd_data;
assign VX_fwd_rsp.src2_fwd_data = out_src2_fwd_data;
wire exe_mem_read;
wire mem_mem_read;
@@ -55,16 +58,12 @@ module VX_forwarding (
wire exe_jal;
wire mem_jal;
wire wb_jal ;
wire exe_csr;
wire mem_csr;
wire src1_exe_fwd;
wire src1_mem_fwd;
wire src1_wb_fwd;
wire src2_exe_fwd;
wire src2_mem_fwd;
wire src2_wb_fwd;
wire csr_exe_fwd;
wire csr_mem_fwd;
wire[`NT_M1:0][31:0] use_execute_PC_next;
wire[`NT_M1:0][31:0] use_memory_PC_next;
@@ -90,8 +89,6 @@ module VX_forwarding (
assign mem_jal = (in_memory_wb == `WB_JAL);
assign wb_jal = (in_writeback_wb == `WB_JAL);
assign exe_csr = (in_execute_is_csr == 1'b1);
assign mem_csr = (in_memory_is_csr == 1'b1);
// SRC1
@@ -144,12 +141,6 @@ module VX_forwarding (
// CSR
assign csr_exe_fwd = (in_decode_csr_address == in_execute_csr_address) && exe_csr;
assign csr_mem_fwd = (in_decode_csr_address == in_memory_csr_address) && mem_csr && !csr_exe_fwd;
assign out_csr_fwd = csr_exe_fwd || csr_mem_fwd; // COMMENT
wire exe_mem_read_stall = ((src1_exe_fwd || src2_exe_fwd) && exe_mem_read) ? `STALL : `NO_STALL;
wire mem_mem_read_stall = ((src1_mem_fwd || src2_mem_fwd) && mem_mem_read) ? `STALL : `NO_STALL;
@@ -170,10 +161,6 @@ module VX_forwarding (
( src2_wb_fwd ) ? (wb_jal ? use_writeback_PC_next : (wb_mem_read ? in_writeback_mem_data : in_writeback_alu_result)) :
in_execute_alu_result; // last one should be deadbeef
assign out_csr_fwd_data = csr_exe_fwd ? in_execute_alu_result[0][31:0] :
csr_mem_fwd ? in_memory_csr_result[31:0] :
in_execute_alu_result[0][31:0]; // last one should be deadbeef