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cache optimization - moved read requests to stage1 and eliminating stage3

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This commit is contained in:
Blaise Tine
2020-12-31 07:40:58 -08:00
parent 9f128085d5
commit abe32ed553
16 changed files with 301 additions and 355 deletions
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15
hw/rtl/VX_mem_unit.v
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@@ -136,10 +136,7 @@ module VX_mem_unit # (
.dram_rsp_valid (icache_dram_rsp_if.valid),
.dram_rsp_data (icache_dram_rsp_if.data),
.dram_rsp_tag (icache_dram_rsp_if.tag),
.dram_rsp_ready (icache_dram_rsp_if.ready),
// Miss status
`UNUSED_PIN (miss_vec)
.dram_rsp_ready (icache_dram_rsp_if.ready)
);
VX_cache #(
@@ -197,10 +194,7 @@ module VX_mem_unit # (
.dram_rsp_valid (dcache_dram_rsp_if.valid),
.dram_rsp_data (dcache_dram_rsp_if.data),
.dram_rsp_tag (dcache_dram_rsp_if.tag),
.dram_rsp_ready (dcache_dram_rsp_if.ready),
// Miss status
`UNUSED_PIN (miss_vec)
.dram_rsp_ready (dcache_dram_rsp_if.ready)
);
if (`SM_ENABLE) begin
@@ -260,10 +254,7 @@ module VX_mem_unit # (
.dram_rsp_valid (0),
.dram_rsp_data (0),
.dram_rsp_tag (0),
`UNUSED_PIN (dram_rsp_ready),
// Miss status
`UNUSED_PIN (miss_vec)
`UNUSED_PIN (dram_rsp_ready)
);
end