From abca2f7abb3db6068075d043cb15ac473b9594bb Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Sun, 1 Mar 2020 22:27:18 -0800 Subject: [PATCH] Modified Scheduler to be mask based (allows thread granuility writebacks) + Fixed all LW and SW unit test errors errors --- rtl/VX_scheduler.v | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/rtl/VX_scheduler.v b/rtl/VX_scheduler.v index da9962a6..a3116744 100644 --- a/rtl/VX_scheduler.v +++ b/rtl/VX_scheduler.v @@ -17,13 +17,14 @@ module VX_scheduler ( - reg[31:0] rename_table[`NW-1:0]; + reg[31:0][`NT-1:0] rename_table[`NW-1:0]; wire valid_wb = (VX_writeback_inter.wb != 0) && (|VX_writeback_inter.wb_valid) && (VX_writeback_inter.rd != 0); wire wb_inc = (VX_bckE_req.wb != 0) && (VX_bckE_req.rd != 0); - wire rs1_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rs1]; - wire rs2_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rs2]; + wire rs1_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rs1] != 0; + wire rs2_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rs2] != 0; + wire rd_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rd ] != 0; wire is_store = (VX_bckE_req.mem_write != `NO_MEM_WRITE); wire is_load = (VX_bckE_req.mem_read != `NO_MEM_READ); @@ -35,19 +36,18 @@ module VX_scheduler ( wire is_exec = !is_mem && !is_gpu && !is_csr; - wire rs1_pass = ((valid_wb && (VX_writeback_inter.rd == VX_bckE_req.rs1))); - wire rs2_pass = ((valid_wb && (VX_writeback_inter.rd == VX_bckE_req.rs2))); // wire rs1_pass = 0; // wire rs2_pass = 0; wire using_rs2 = (VX_bckE_req.rs2_src == `RS2_REG) || is_store || VX_bckE_req.is_barrier || VX_bckE_req.is_wspawn; - wire rs1_rename_qual = ((rs1_rename || (rs1_pass && 0)) && (VX_bckE_req.rs1 != 0)); - wire rs2_rename_qual = ((rs2_rename || (rs2_pass && 0)) && (VX_bckE_req.rs2 != 0 && using_rs2)); + wire rs1_rename_qual = ((rs1_rename) && (VX_bckE_req.rs1 != 0)); + wire rs2_rename_qual = ((rs2_rename) && (VX_bckE_req.rs2 != 0 && using_rs2)); + wire rd_rename_qual = ((rd_rename ) && (VX_bckE_req.rd != 0)); - wire rename_valid = rs1_rename_qual || rs2_rename_qual ; + wire rename_valid = rs1_rename_qual || rs2_rename_qual || rd_rename_qual; assign schedule_delay = ((rename_valid) && (|VX_bckE_req.valid)) || (memory_delay && is_mem) @@ -67,8 +67,8 @@ module VX_scheduler ( end end end else begin - if (valid_wb ) rename_table[VX_writeback_inter.wb_warp_num][VX_writeback_inter.rd] <= 0; - if (!schedule_delay && wb_inc) rename_table[VX_bckE_req.warp_num ][VX_bckE_req.rd] <= 1; + if (valid_wb ) rename_table[VX_writeback_inter.wb_warp_num][VX_writeback_inter.rd] <= rename_table[VX_writeback_inter.wb_warp_num][VX_writeback_inter.rd] & (~VX_writeback_inter.wb_valid); + if (!schedule_delay && wb_inc) rename_table[VX_bckE_req.warp_num ][VX_bckE_req.rd ] <= VX_bckE_req.valid; end end