cache request interfaces update

hw/rtl/interfaces/VX_cache_core_rsp_if.v

@@ -1,20 +0,0 @@
-`ifndef VX_CACHE_CORE_RSP_IF
-`define VX_CACHE_CORE_RSP_IF
-
-`include "../cache/VX_cache_config.vh"
-
-interface VX_cache_core_rsp_if #(
-    parameter NUM_REQS         = 1,
-    parameter WORD_SIZE        = 1,
-    parameter CORE_TAG_WIDTH   = 1,
-    parameter CORE_TAG_ID_BITS = 0
-) ();
-
-    wire [NUM_REQS-1:0]                                valid;    
-    wire [NUM_REQS-1:0][`WORD_WIDTH-1:0]               data;
-    wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] tag;    
-    wire                                               ready;      
-
-endinterface
-
-`endif

hw/rtl/interfaces/VX_dcache_core_req_if.v

@@ -1,9 +1,9 @@
-`ifndef VX_CACHE_CORE_REQ_IF
-`define VX_CACHE_CORE_REQ_IF
+`ifndef VX_DCACHE_CORE_REQ_IF
+`define VX_DCACHE_CORE_REQ_IF
 
 `include "../cache/VX_cache_config.vh"
 
-interface VX_cache_core_req_if #(
+interface VX_dcache_core_req_if #(
     parameter NUM_REQS         = 1,
     parameter WORD_SIZE        = 1,
     parameter CORE_TAG_WIDTH   = 1,

hw/rtl/interfaces/VX_dcache_core_rsp_if.v

@@ -0,0 +1,20 @@
+`ifndef VX_DCACHE_CORE_RSP_IF
+`define VX_DCACHE_CORE_RSP_IF
+
+`include "../cache/VX_cache_config.vh"
+
+interface VX_dcache_core_rsp_if #(
+    parameter NUM_REQS         = 1,
+    parameter WORD_SIZE        = 1,
+    parameter CORE_TAG_WIDTH   = 1,
+    parameter CORE_TAG_ID_BITS = 0
+) ();
+
+    wire [NUM_REQS-1:0]                     valid;    
+    wire [NUM_REQS-1:0][`WORD_WIDTH-1:0]    data;
+    wire [CORE_TAG_WIDTH-1:0]               tag;    
+    wire                                    ready;      
+
+endinterface
+
+`endif

hw/rtl/interfaces/VX_icache_core_req_if.v

@@ -0,0 +1,19 @@
+`ifndef VX_ICACHE_CORE_REQ_IF
+`define VX_ICACHE_CORE_REQ_IF
+
+`include "../cache/VX_cache_config.vh"
+
+interface VX_icache_core_req_if #(
+    parameter WORD_SIZE        = 1,
+    parameter CORE_TAG_WIDTH   = 1,
+    parameter CORE_TAG_ID_BITS = 0
+) ();
+
+    wire                        valid;
+    wire [`WORD_ADDR_WIDTH-1:0] addr;
+    wire [CORE_TAG_WIDTH-1:0]   tag;    
+    wire                        ready;
+
+endinterface
+
+`endif

hw/rtl/interfaces/VX_icache_core_rsp_if.v

@@ -0,0 +1,19 @@
+`ifndef VX_ICACHE_CORE_RSP_IF
+`define VX_ICACHE_CORE_RSP_IF
+
+`include "../cache/VX_cache_config.vh"
+
+interface VX_icache_core_rsp_if #(
+    parameter WORD_SIZE        = 1,
+    parameter CORE_TAG_WIDTH   = 1,
+    parameter CORE_TAG_ID_BITS = 0
+) ();
+
+    wire                        valid;    
+    wire [`WORD_WIDTH-1:0]      data;
+    wire [CORE_TAG_WIDTH-1:0]   tag;    
+    wire                        ready;      
+
+endinterface
+
+`endif

hw/rtl/interfaces/VX_lsu_req_if.v

@@ -14,7 +14,7 @@ interface VX_lsu_req_if ();
     wire [`NUM_THREADS-1:0][31:0]   base_addr;    
     wire [31:0]                     offset;
     wire [`NR_BITS-1:0]             rd;
-    wire                            wb;        
+    wire                            wb;
     wire                            ready;
 
 endinterface