Passing some cases
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@@ -69,11 +69,11 @@ module VX_cache_req_queue (
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wire push_qual = reqq_push && !reqq_full;
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wire pop_qual = reqq_pop && use_empty && !out_empty && !reqq_empty;
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VX_generic_queue #(.DATAW(`NUMBER_REQUESTS * (1+32+32+5+2+(`NW_M1+1)+3+3)), .SIZE(`REQQ_SIZE)) reqq_queue(
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VX_generic_queue #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue(
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.clk (clk),
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.reset (reset),
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.push (push_qual),
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.in_data ({bank_valids, bank_addr, bank_writedata, bank_rd, bank_wb, bank_warp_num, bank_mem_read, bank_mem_write}),
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.in_data ({bank_valids , bank_addr , bank_writedata , bank_rd , bank_wb , bank_warp_num , bank_mem_read , bank_mem_write}),
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.pop (pop_qual),
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.out_data({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write}),
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.empty (reqq_empty),
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@@ -82,7 +82,7 @@ module VX_cache_req_queue (
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assign qual_valids = use_empty ? out_per_valids : use_per_valids;
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assign qual_valids = use_empty ? out_per_valids : out_empty ? 0 : use_per_valids;
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assign qual_addr = use_empty ? out_per_addr : use_per_addr;
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assign qual_writedata = use_empty ? out_per_writedata : use_per_writedata;
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assign qual_rd = use_empty ? out_per_rd : use_per_rd;
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@@ -105,13 +105,13 @@ module VX_cache_req_queue (
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assign reqq_req_writedata_st0 = qual_writedata[qual_request_index];
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assign reqq_req_rd_st0 = qual_rd;
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assign reqq_req_wb_st0 = qual_wb;
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assign reqq_req_warp_num_st0 = qual_warp_num
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assign reqq_req_warp_num_st0 = qual_warp_num;
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assign reqq_req_mem_read_st0 = qual_mem_read;
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assign reqq_req_mem_write_st0 = qual_mem_write;
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assign updated_valids = qual_valids & (~(1 << qual_request_index));
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always @(posedge clk or reset) begin
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always @(posedge clk) begin
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if (reset) begin
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use_per_valids <= 0;
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use_per_addr <= 0;
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@@ -131,6 +131,8 @@ module VX_cache_req_queue (
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use_per_warp_num <= qual_warp_num;
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use_per_mem_read <= qual_mem_read;
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use_per_mem_write <= qual_mem_write;
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end else if (reqq_pop) begin
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use_per_valids[qual_request_index] <= updated_valids;
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end
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end
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end
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