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Passing some cases

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This commit is contained in:
felsabbagh3
2020-03-04 04:05:54 -08:00
parent d8e25045be
commit aa1a0ee376
22 changed files with 217 additions and 153 deletions
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16
rtl/VX_cache/VX_cache_dram_req_arb.v
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@@ -12,10 +12,10 @@ module VX_cache_dram_req_arb (
input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr,
// DFQ Request
output wire[`NUMBER_BANKS-1] per_bank_dram_wb_queue_pop,
input wire[`NUMBER_BANKS-1] per_bank_dram_wb_req,
input wire[`NUMBER_BANKS-1][31:0] per_bank_dram_wb_req_addr,
input wire[`NUMBER_BANKS-1][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data,
output wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop,
input wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req,
input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr,
input wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data,
// real Dram request
output wire dram_req,
@@ -29,10 +29,10 @@ module VX_cache_dram_req_arb (
wire dfqq_req;
wire dfqq_req_addr;
wire[31:0] dfqq_req_addr;
wire dfqq_empty;
wire dfqq_pop = !dwb_valid && dfqq_req; // If no dwb, and dfqq has valids, then pop
wire dfqq_push = (|per_bank_dram_wb_queue_pop);
wire dfqq_push = (|per_bank_dram_fill_req);
VX_cache_dfq_queue VX_cache_dfq_queue(
.clk (clk),
.reset (reset),
@@ -48,7 +48,7 @@ module VX_cache_dram_req_arb (
wire dwb_valid;
wire[`vx_log2(`NUMBER_BANKS)-1:0] dwb_bank;
wire[`vx_clog2(`NUMBER_BANKS)-1:0] dwb_bank;
VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_dwb(
.valids(per_bank_dram_wb_req),
.index (dwb_bank),
@@ -62,7 +62,7 @@ module VX_cache_dram_req_arb (
assign dram_req = dwb_valid || dfqq_req;
assign dram_req_write = dwb_valid;
assign dram_req_read = dfqq_req && !dwb_valid;
assign dram_req_addr = dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr;
assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr) & `BASE_ADDR_MASK;
assign dram_req_size = `BANK_LINE_SIZE_BYTES;
assign dram_req_data = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0;