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fixed snoop forwarding bug and single bank support

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This commit is contained in:
Blaise Tine
2020-05-24 04:29:43 -04:00
parent 47ed6b18ff
commit a9f896b4f3
9 changed files with 17572 additions and 33364 deletions
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4
driver/rtlsim/Makefile
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@@ -15,8 +15,8 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
#DBG_PRINT=$(DBG_PRINT_FLAGS) #DBG_PRINT=$(DBG_PRINT_FLAGS)
#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4 #MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4
MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4 #MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4
#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
#DEBUG = 1 #DEBUG = 1

50749
driver/tests/demo/run.log
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File diff suppressed because it is too large Load Diff

2
hw/rtl/VX_config.vh
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@@ -158,7 +158,7 @@
// Number of banks {1, 2, 4, 8,...} // Number of banks {1, 2, 4, 8,...}
`ifndef INUM_BANKS `ifndef INUM_BANKS
`define INUM_BANKS 8 `define INUM_BANKS 1
`endif `endif
// Size of a word in bytes // Size of a word in bytes

30
hw/rtl/cache/VX_bank.v vendored
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@@ -714,15 +714,29 @@ module VX_bank #(
|| dram_fill_req_stall; || dram_fill_req_stall;
`ifdef DBG_PRINT_CACHE_BANK `ifdef DBG_PRINT_CACHE_BANK
always_ff @(posedge clk) begin if (NUM_BANKS == 1) begin
if (dram_fill_req_valid && dram_fill_req_ready) begin always_ff @(posedge clk) begin
$display("%t: bank%02d:%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID)); if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%02d:%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, dram_fill_req_addr);
end
if (dram_wb_req_valid && dram_wb_req_ready) begin
$display("%t: bank%02d:%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, dram_wb_req_addr, dram_wb_req_data);
end
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%02d:%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, dram_fill_rsp_addr, dram_fill_rsp_data);
end
end end
if (dram_wb_req_valid && dram_wb_req_ready) begin end else begin
$display("%t: bank%02d:%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data); always_ff @(posedge clk) begin
end if (dram_fill_req_valid && dram_fill_req_ready) begin
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin $display("%t: bank%02d:%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
$display("%t: bank%02d:%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data); end
if (dram_wb_req_valid && dram_wb_req_ready) begin
$display("%t: bank%02d:%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data);
end
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%02d:%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
end
end end
end end
`endif `endif

38
hw/rtl/cache/VX_cache.v vendored
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@@ -287,25 +287,43 @@ module VX_cache #(
assign per_bank_core_rsp_data [i] = curr_bank_core_rsp_data; assign per_bank_core_rsp_data [i] = curr_bank_core_rsp_data;
// Dram fill request // Dram fill request
assign per_bank_dram_fill_req_valid[i] = curr_bank_dram_fill_req_valid; assign per_bank_dram_fill_req_valid[i] = curr_bank_dram_fill_req_valid;
assign per_bank_dram_fill_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_fill_req_addr, i); if (NUM_BANKS == 1) begin
assign curr_bank_dram_fill_req_ready = dram_fill_req_ready; assign per_bank_dram_fill_req_addr[i] = curr_bank_dram_fill_req_addr;
end else begin
assign per_bank_dram_fill_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_fill_req_addr, i);
end
assign curr_bank_dram_fill_req_ready = dram_fill_req_ready;
// Dram fill response // Dram fill response
assign curr_bank_dram_fill_rsp_valid = dram_rsp_valid && (`DRAM_ADDR_BANK(dram_rsp_tag) == i); if (NUM_BANKS == 1) begin
assign curr_bank_dram_fill_rsp_addr = `DRAM_TO_LINE_ADDR(dram_rsp_tag); assign curr_bank_dram_fill_rsp_valid = dram_rsp_valid;
assign curr_bank_dram_fill_rsp_addr = dram_rsp_tag;
end else begin
assign curr_bank_dram_fill_rsp_valid = dram_rsp_valid && (`DRAM_ADDR_BANK(dram_rsp_tag) == i);
assign curr_bank_dram_fill_rsp_addr = `DRAM_TO_LINE_ADDR(dram_rsp_tag);
end
assign curr_bank_dram_fill_rsp_data = dram_rsp_data; assign curr_bank_dram_fill_rsp_data = dram_rsp_data;
assign per_bank_dram_fill_rsp_ready[i] = curr_bank_dram_fill_rsp_ready; assign per_bank_dram_fill_rsp_ready[i] = curr_bank_dram_fill_rsp_ready;
// Dram writeback request // Dram writeback request
assign per_bank_dram_wb_req_valid[i] = curr_bank_dram_wb_req_valid; assign per_bank_dram_wb_req_valid[i] = curr_bank_dram_wb_req_valid;
assign per_bank_dram_wb_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_wb_req_addr, i); if (NUM_BANKS == 1) begin
assign per_bank_dram_wb_req_data[i] = curr_bank_dram_wb_req_data; assign per_bank_dram_wb_req_addr[i] = curr_bank_dram_wb_req_addr;
assign curr_bank_dram_wb_req_ready = per_bank_dram_wb_req_ready[i]; end else begin
assign per_bank_dram_wb_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_wb_req_addr, i);
end
assign per_bank_dram_wb_req_data[i] = curr_bank_dram_wb_req_data;
assign curr_bank_dram_wb_req_ready = per_bank_dram_wb_req_ready[i];
// Snoop request // Snoop request
assign curr_bank_snp_req_valid = snp_req_valid_qual && (`DRAM_ADDR_BANK(snp_req_addr_qual) == i); if (NUM_BANKS == 1) begin
assign curr_bank_snp_req_addr = `DRAM_TO_LINE_ADDR(snp_req_addr_qual); assign curr_bank_snp_req_valid = snp_req_valid_qual;
assign curr_bank_snp_req_addr = snp_req_addr_qual;
end else begin
assign curr_bank_snp_req_valid = snp_req_valid_qual && (`DRAM_ADDR_BANK(snp_req_addr_qual) == i);
assign curr_bank_snp_req_addr = `DRAM_TO_LINE_ADDR(snp_req_addr_qual);
end
assign curr_bank_snp_req_tag = snp_req_tag_qual; assign curr_bank_snp_req_tag = snp_req_tag_qual;
assign per_bank_snp_req_ready[i] = curr_bank_snp_req_ready; assign per_bank_snp_req_ready[i] = curr_bank_snp_req_ready;

18
hw/rtl/cache/VX_cache_core_req_bank_sel.v vendored
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@@ -12,18 +12,24 @@ module VX_cache_core_req_bank_sel #(
parameter NUM_REQUESTS = 0 parameter NUM_REQUESTS = 0
) ( ) (
input wire [NUM_REQUESTS-1:0] core_req_valid, input wire [NUM_REQUESTS-1:0] core_req_valid,
`IGNORE_WARNINGS_BEGIN
input wire [NUM_REQUESTS-1:0][31:0] core_req_addr, input wire [NUM_REQUESTS-1:0][31:0] core_req_addr,
`IGNORE_WARNINGS_END
output reg [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids output reg [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids
); );
integer i; integer i;
always @(*) begin if (NUM_BANKS == 1) begin
per_bank_valids = 0; always @(*) begin
for (i = 0; i < NUM_REQUESTS; i++) begin per_bank_valids = 0;
if (NUM_BANKS == 1) begin for (i = 0; i < NUM_REQUESTS; i++) begin
// If there is only one bank, then only map requests to that bank
per_bank_valids[0][i] = core_req_valid[i]; per_bank_valids[0][i] = core_req_valid[i];
end else begin end
end
end else begin
always @(*) begin
per_bank_valids = 0;
for (i = 0; i < NUM_REQUESTS; i++) begin
per_bank_valids[core_req_addr[i][`BANK_SELECT_ADDR_RNG]][i] = core_req_valid[i]; per_bank_valids[core_req_addr[i][`BANK_SELECT_ADDR_RNG]][i] = core_req_valid[i];
end end
end end

37
hw/rtl/cache/VX_cache_miss_resrv.v vendored
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@@ -156,18 +156,35 @@ module VX_cache_miss_resrv #(
`ifdef DBG_PRINT_CACHE_MSRQ `ifdef DBG_PRINT_CACHE_MSRQ
integer j; integer j;
always_ff @(posedge clk) begin if (NUM_BANKS == 1) begin
if (mrvq_push || mrvq_pop) begin always_ff @(posedge clk) begin
$write("%t: bank%02d:%01d msrq: push=%b pop=%b", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop); if (mrvq_push || mrvq_pop) begin
for (j = 0; j < MRVQ_SIZE; j++) begin $write("%t: bank%02d:%01d msrq: push=%b pop=%b", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop);
if (valid_table[j]) begin for (j = 0; j < MRVQ_SIZE; j++) begin
$write(" "); if (valid_table[j]) begin
if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*"); $write(" ");
if (~ready_table[j]) $write("!"); if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*");
$write("addr%0d=%0h", j, `LINE_TO_BYTE_ADDR(addr_table[j], BANK_ID)); if (~ready_table[j]) $write("!");
$write("addr%0d=%0h", j, {addr_table[j], `BASE_ADDR_BITS'(0)});
end
end end
$write("\n");
end
end
end else begin
always_ff @(posedge clk) begin
if (mrvq_push || mrvq_pop) begin
$write("%t: bank%02d:%01d msrq: push=%b pop=%b", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop);
for (j = 0; j < MRVQ_SIZE; j++) begin
if (valid_table[j]) begin
$write(" ");
if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*");
if (~ready_table[j]) $write("!");
$write("addr%0d=%0h", j, `LINE_TO_BYTE_ADDR(addr_table[j], BANK_ID));
end
end
$write("\n");
end end
$write("\n");
end end
end end
`endif `endif

40
hw/rtl/cache/VX_snp_forwarder.v vendored
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@@ -34,11 +34,13 @@ module VX_snp_forwarder #(
output wire [NUM_REQUESTS-1:0] snp_fwdin_ready output wire [NUM_REQUESTS-1:0] snp_fwdin_ready
); );
reg [`DRAM_ADDR_WIDTH+SNP_REQ_TAG_WIDTH-1:0] pending_reqs [SNRQ_SIZE-1:0]; reg [`DRAM_ADDR_WIDTH+SNP_REQ_TAG_WIDTH-1:0] pending_reqs [SNRQ_SIZE-1:0];
reg [`REQS_BITS-1:0] pending_cntrs [SNRQ_SIZE-1:0]; reg [`REQS_BITS:0] pending_cntrs [SNRQ_SIZE-1:0];
reg [`LOG2UP(SNRQ_SIZE)-1:0] rd_ptr, wr_ptr; reg [`LOG2UP(SNRQ_SIZE):0] rd_ptr, wr_ptr;
reg [`LOG2UP(SNRQ_SIZE)-1:0] pending_size;
reg [`REQS_BITS-1:0] fwdin_sel; reg [`REQS_BITS-1:0] fwdin_sel;
wire enqueue, dequeue, empty;
wire [`LOG2UP(SNRQ_SIZE)-1:0] rd_a, wr_a;
wire enqueue, dequeue, empty, full;
wire fwdout_ready; wire fwdout_ready;
@@ -49,47 +51,43 @@ module VX_snp_forwarder #(
assign fwdout_ready = (& snp_fwdout_ready); assign fwdout_ready = (& snp_fwdout_ready);
assign snp_req_ready = (pending_size != `LOG2UP(SNRQ_SIZE)'(SNRQ_SIZE-1)) // not full assign snp_req_ready = !full && fwdout_ready;
&& fwdout_ready;
assign rd_a = rd_ptr[`LOG2UP(SNRQ_SIZE)-1:0];
assign wr_a = wr_ptr[`LOG2UP(SNRQ_SIZE)-1:0];
genvar i; genvar i;
for (i = 0; i < NUM_REQUESTS; i++) begin for (i = 0; i < NUM_REQUESTS; i++) begin
assign snp_fwdout_valid[i] = enqueue && fwdout_ready; assign snp_fwdout_valid[i] = enqueue && fwdout_ready;
assign snp_fwdout_addr[i] = snp_req_addr; assign snp_fwdout_addr[i] = snp_req_addr;
assign snp_fwdout_tag[i] = wr_ptr; assign snp_fwdout_tag[i] = wr_a;
end end
assign fwdin_ready = snp_rsp_ready; assign fwdin_ready = snp_rsp_ready;
assign fwdin_taken = fwdin_valid && fwdin_ready; assign fwdin_taken = fwdin_valid && fwdin_ready;
assign snp_rsp_valid = fwdin_taken && (1 == pending_cntrs[fwdin_tag]); // send response assign snp_rsp_valid = fwdin_taken && (1 == pending_cntrs[fwdin_tag]); // send response
assign {snp_rsp_addr, snp_rsp_tag} = pending_reqs[fwdin_tag]; assign {snp_rsp_addr, snp_rsp_tag} = pending_reqs[fwdin_tag];
assign empty = (wr_ptr == rd_ptr); assign empty = (wr_ptr == rd_ptr);
assign full = (wr_a == rd_a) && (wr_ptr[`LOG2UP(SNRQ_SIZE)] != rd_ptr[`LOG2UP(SNRQ_SIZE)]);
assign enqueue = snp_req_valid && snp_req_ready; assign enqueue = snp_req_valid && snp_req_ready;
assign dequeue = !empty && (0 == pending_cntrs[rd_ptr]); assign dequeue = !empty && (0 == pending_cntrs[rd_a]);
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
rd_ptr <= 0; rd_ptr <= 0;
wr_ptr <= 0; wr_ptr <= 0;
pending_size <= 0;
end else begin end else begin
if (enqueue) begin if (enqueue) begin
pending_reqs[wr_ptr] <= {snp_req_addr, snp_req_tag}; pending_reqs[wr_a] <= {snp_req_addr, snp_req_tag};
pending_cntrs[wr_ptr] <= `REQS_BITS'(NUM_REQUESTS); pending_cntrs[wr_a] <= NUM_REQUESTS;
wr_ptr <= wr_ptr + 1; wr_ptr <= wr_ptr + 1;
if (!dequeue) begin
pending_size <= pending_size + 1;
end
end end
if (dequeue) begin if (dequeue) begin
rd_ptr <= rd_ptr + 1; rd_ptr <= rd_ptr + 1;
if (!enqueue) begin
pending_size <= pending_size - 1;
end
end end
if (fwdin_taken) begin if (fwdin_taken) begin
pending_cntrs[fwdin_tag] <= pending_cntrs[fwdin_tag] - 1; pending_cntrs[fwdin_tag] <= pending_cntrs[fwdin_tag] - 1;

8
hw/simulate/simulator.cpp
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@@ -190,6 +190,10 @@ void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
int pending_snp_reqs = 1; int pending_snp_reqs = 1;
#ifdef DBG_PRINT_CACHE_SNP
std::cout << timestamp << ": [sim] snp req: addr=" << std::hex << vortex_->snp_req_addr << std::dec << " tag=" << vortex_->snp_req_tag << " remain=" << (aligned_addr_end - vortex_->snp_req_addr - 1) << std::endl;
#endif
for (;;) { for (;;) {
this->step(); this->step();
if (vortex_->snp_rsp_valid) { if (vortex_->snp_rsp_valid) {
@@ -200,12 +204,12 @@ void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
#endif #endif
} }
if (vortex_->snp_req_valid && vortex_->snp_req_ready) { if (vortex_->snp_req_valid && vortex_->snp_req_ready) {
if (vortex_->snp_req_addr < aligned_addr_end) { if (vortex_->snp_req_addr + 1 < aligned_addr_end) {
vortex_->snp_req_addr += 1; vortex_->snp_req_addr += 1;
vortex_->snp_req_tag += 1; vortex_->snp_req_tag += 1;
++pending_snp_reqs; ++pending_snp_reqs;
#ifdef DBG_PRINT_CACHE_SNP #ifdef DBG_PRINT_CACHE_SNP
std::cout << timestamp << ": [sim] snp req: addr=" << vortex_->snp_req_addr << " tag=" << vortex_->snp_req_tag << " remain=" << (aligned_addr_end - vortex_->snp_req_addr) << std::endl; std::cout << timestamp << ": [sim] snp req: addr=" << std::hex << vortex_->snp_req_addr << std::dec << " tag=" << vortex_->snp_req_tag << " remain=" << (aligned_addr_end - vortex_->snp_req_addr - 1) << std::endl;
#endif #endif
} else { } else {
vortex_->snp_req_valid = 0; vortex_->snp_req_valid = 0;