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minor tweaks to appease quartus

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re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support
This commit is contained in:
wgulian3
2020-03-10 04:05:01 -04:00
parent ca62e57a0d
commit a931b588c2
5 changed files with 23 additions and 20 deletions
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16
rtl/VX_cache/VX_bank.v
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@@ -296,17 +296,19 @@ module VX_bank
);
wire stall_bank_pipe;
reg is_fill_in_pipe;
reg is_fill_in_pipe;
genvar p_stage;
reg[16:0] p_stage;
always @(*) begin
assign is_fill_in_pipe = 0;
is_fill_in_pipe = 0;
for (p_stage = 0; p_stage < STAGE_1_CYCLES; p_stage=p_stage+1) begin
if (is_fill_st1[p_stage]) assign is_fill_in_pipe = 1;
if (is_fill_st1[p_stage]) is_fill_in_pipe = 1;
end
if (is_fill_st2) assign is_fill_in_pipe = 1;
if (is_fill_st2) is_fill_in_pipe = 1;
end
// assign is_fill_in_pipe = (|is_fill_st1) || is_fill_st2;
assign dfpq_pop = !dfpq_empty && !stall_bank_pipe && !dfpq_hazard_st0;
@@ -630,7 +632,7 @@ module VX_bank
assign stall_bank_pipe = (is_snp_st2 && valid_st2 && ffsq_full) || ((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full);
endmodule
endmodule : VX_bank