From a8d063e9ad101b82de494283a52614dc43328b86 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Mon, 28 Oct 2019 13:43:12 -0400 Subject: [PATCH] Synthesis Cleanup 1 --- rtl/VX_define.v | 1 + rtl/VX_gpr_wrapper.v | 4 +- rtl/VX_warp_scheduler.v | 19 +- rtl/Vortex.v | 11 +- rtl/byte_enabled_simple_dual_port_ram.v | 2 +- rtl/cache/VX_cache_data.v | 49 +- rtl/cache/VX_d_cache.v | 17 +- rtl/shared_memory/VX_priority_encoder_sm.v | 2 +- rtl/shared_memory/VX_shared_memory_block.v | 2 +- syn/Makefile | 2 +- syn/fsyn.tcl | 2 + syn/vortex_syn.log | 2531 ++++++++++++++++++++ 12 files changed, 2602 insertions(+), 40 deletions(-) create mode 100644 syn/vortex_syn.log diff --git a/rtl/VX_define.v b/rtl/VX_define.v index 09af7bba..76b28823 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -115,6 +115,7 @@ `define ZERO_REG 5'h0 +// `define PARAM // Offset `define CACHE_OFFSET_NB ($clog2(NUM_WORDS_PER_BLOCK)) diff --git a/rtl/VX_gpr_wrapper.v b/rtl/VX_gpr_wrapper.v index a796e19f..b9325eb2 100644 --- a/rtl/VX_gpr_wrapper.v +++ b/rtl/VX_gpr_wrapper.v @@ -17,7 +17,9 @@ module VX_gpr_wrapper ( wire[`NT_M1:0][31:0] jal_data; genvar index; - for (index = 0; index <= `NT_M1; index = index + 1) assign jal_data[index] = VX_gpr_jal.curr_PC; + for (index = 0; index <= `NT_M1; index = index + 1) begin + assign jal_data[index] = VX_gpr_jal.curr_PC; + end assign out_a_reg_data = (VX_gpr_jal.is_jal ? jal_data : (temp_a_reg_data[VX_gpr_read.warp_num])); diff --git a/rtl/VX_warp_scheduler.v b/rtl/VX_warp_scheduler.v index eb449a01..016e9c91 100644 --- a/rtl/VX_warp_scheduler.v +++ b/rtl/VX_warp_scheduler.v @@ -122,7 +122,7 @@ module VX_warp_scheduler ( visible_active[0] <= 1; // Activating first warp thread_masks[0] <= 1; // Activating first thread in first warp warp_stalled <= 0; - total_barrier_stall = 0; + // total_barrier_stall = 0; for (curr_w_help = 1; curr_w_help < `NW; curr_w_help=curr_w_help+1) begin warp_pcs[curr_w_help] <= 0; warp_active[curr_w_help] <= 0; // Activating first warp @@ -217,14 +217,15 @@ module VX_warp_scheduler ( assign wstall_this_cycle = wstall && (wstall_warp_num == warp_to_schedule); // Maybe bug - integer curr_b; - always @(*) begin - total_barrier_stall = 0; - for (curr_b = 0; curr_b < `NUM_BARRIERS; curr_b=curr_b+1) - begin - total_barrier_stall[`NW-1:0] = total_barrier_stall[`NW-1:0] | barrier_stall_mask[curr_b[($clog2(`NUM_BARRIERS)-1):0]][`NW-1:0]; - end - end + assign total_barrier_stall = barrier_stall_mask[0] | barrier_stall_mask[1] | barrier_stall_mask[2] | barrier_stall_mask[3]; + // integer curr_b; + // always @(*) begin + // total_barrier_stall = 0; + // for (curr_b = 0; curr_b < `NUM_BARRIERS; curr_b=curr_b+1) + // begin + // total_barrier_stall[`NW-1:0] = total_barrier_stall[`NW-1:0] | barrier_stall_mask[curr_b]; + // end + // end assign update_visible_active = (count_visible_active < 1) && !(stall || wstall_this_cycle || hazard || is_join); diff --git a/rtl/Vortex.v b/rtl/Vortex.v index b956c759..d476e7c4 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -8,8 +8,7 @@ module Vortex parameter CACHE_WAYS = 1, parameter CACHE_BLOCK = 128, // Bytes parameter CACHE_BANKS = 8, - localparam NUMBER_BANKS = 8, - localparam NUM_WORDS_PER_BLOCK = 4 + parameter NUM_WORDS_PER_BLOCK = 4 ) ( input wire clk, @@ -23,15 +22,17 @@ module Vortex output reg [31:0] o_m_read_addr, output reg [31:0] o_m_evict_addr, output reg o_m_valid, - output reg [31:0] o_m_writedata[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0], + output reg [31:0] o_m_writedata[CACHE_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0], output reg o_m_read_or_write, // Rsp - input wire [31:0] i_m_readdata[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0], + input wire [31:0] i_m_readdata[CACHE_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0], input wire i_m_ready, output wire out_ebreak ); + + wire memory_delay; wire gpr_stage_delay; wire schedule_delay; @@ -58,7 +59,7 @@ assign VX_dram_req_rsp.i_m_ready = i_m_ready; genvar curr_bank; genvar curr_word; -for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank = curr_bank + 1) begin +for (curr_bank = 0; curr_bank < CACHE_BANKS; curr_bank = curr_bank + 1) begin for (curr_word = 0; curr_word < NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin assign o_m_writedata[curr_bank][curr_word] = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word]; diff --git a/rtl/byte_enabled_simple_dual_port_ram.v b/rtl/byte_enabled_simple_dual_port_ram.v index 2ff23c8b..7a1173d5 100644 --- a/rtl/byte_enabled_simple_dual_port_ram.v +++ b/rtl/byte_enabled_simple_dual_port_ram.v @@ -25,7 +25,7 @@ module byte_enabled_simple_dual_port_ram integer ini; always@(posedge clk, posedge reset) begin if (reset) begin - for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] = 0; + for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] <= 0; end else if(we) begin integer thread_ind; for (thread_ind = 0; thread_ind <= `NT_M1; thread_ind = thread_ind + 1) begin diff --git a/rtl/cache/VX_cache_data.v b/rtl/cache/VX_cache_data.v index 7827f6cd..292ebb5f 100644 --- a/rtl/cache/VX_cache_data.v +++ b/rtl/cache/VX_cache_data.v @@ -13,20 +13,37 @@ module VX_cache_data ( input wire clk, rst, // Clock - // Addr - input wire[`CACHE_IND_SIZE_RNG] addr, - // WE - input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we, - input wire evict, - // Data - input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data - input wire[`CACHE_TAG_SIZE_RNG] tag_write, + `ifdef PARAM + // Addr + input wire[`CACHE_IND_SIZE_RNG] addr, + // WE + input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we, + input wire evict, + // Data + input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, + input wire[`CACHE_TAG_SIZE_RNG] tag_write, - output wire[`CACHE_TAG_SIZE_RNG] tag_use, - output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use, - output wire valid_use, - output wire dirty_use + output wire[`CACHE_TAG_SIZE_RNG] tag_use, + output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use, + output wire valid_use, + output wire dirty_use + `else + // Addr + input wire[7:0] addr, + // WE + input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we, + input wire evict, + // Data + input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data + input wire[16:0] tag_write, + + + output wire[16:0] tag_use, + output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use, + output wire valid_use, + output wire dirty_use + `endif ); @@ -61,10 +78,10 @@ module VX_cache_data always @(posedge clk, posedge rst) begin : update_all if (rst) begin for (ini_ind = 0; ini_ind < NUMBER_INDEXES; ini_ind=ini_ind+1) begin - data[ini_ind] = 0; - tag[ini_ind] = 0; - valid[ini_ind] = 0; - dirty[ini_ind] = 0; + data[ini_ind] <= 0; + tag[ini_ind] <= 0; + valid[ini_ind] <= 0; + dirty[ini_ind] <= 0; end end else begin if (update_dirty) dirty[addr] <= dirt_new; // WRite Port diff --git a/rtl/cache/VX_d_cache.v b/rtl/cache/VX_d_cache.v index eaf08563..d1893dba 100644 --- a/rtl/cache/VX_d_cache.v +++ b/rtl/cache/VX_d_cache.v @@ -146,14 +146,21 @@ module VX_d_cache .found (valid_per_bank[bid]) ); - always @(*) begin - if (use_write_final_data) new_final_data_read[use_thread_index] = use_data_final_data; - end - // assign new_final_data_read[use_thread_index] = use_write_final_data ? use_data_final_data : 0; assign debug_hit_per_bank_mask[bid] = {NUM_REQ{hit_per_bank[bid]}}; assign threads_serviced_per_bank[bid] = use_mask_per_bank[bid] & debug_hit_per_bank_mask[bid]; end + integer test_bid; + always @(*) begin + new_final_data_read = 0; + for (test_bid=0; test_bid < NUMBER_BANKS; test_bid=test_bid+1) + begin + if (hit_per_bank[test_bid]) begin + new_final_data_read[index_per_bank[test_bid]] = readdata_per_bank[test_bid]; + end + end + end + wire[NUMBER_BANKS - 1 : 0] detect_bank_miss; assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] | @@ -212,7 +219,7 @@ module VX_d_cache always @(posedge clk, posedge rst) begin if (rst) begin final_data_read <= 0; - new_final_data_read = 0; + // new_final_data_read = 0; state <= 0; stored_valid <= 0; // eviction_addr_per_bank <= 0; diff --git a/rtl/shared_memory/VX_priority_encoder_sm.v b/rtl/shared_memory/VX_priority_encoder_sm.v index 976722ad..6fa47ece 100644 --- a/rtl/shared_memory/VX_priority_encoder_sm.v +++ b/rtl/shared_memory/VX_priority_encoder_sm.v @@ -104,7 +104,7 @@ module VX_priority_encoder_sm always @(posedge clk, posedge reset) begin if (reset) begin left_requests <= 0; - serviced = 0; + // serviced = 0; end else begin if (!stall) left_requests <= 0; else left_requests <= new_left_requests; diff --git a/rtl/shared_memory/VX_shared_memory_block.v b/rtl/shared_memory/VX_shared_memory_block.v index 0fb633cd..03afa96b 100644 --- a/rtl/shared_memory/VX_shared_memory_block.v +++ b/rtl/shared_memory/VX_shared_memory_block.v @@ -21,7 +21,7 @@ module VX_shared_memory_block ( if (reset) begin for (curr_ind = 0; curr_ind < 128; curr_ind = curr_ind + 1) begin - shared_memory[curr_ind] = 0; + shared_memory[curr_ind] <= 0; end end else if(shm_write) begin if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0]; diff --git a/syn/Makefile b/syn/Makefile index 722d2c32..1cfe585c 100644 --- a/syn/Makefile +++ b/syn/Makefile @@ -4,4 +4,4 @@ all: syn syn: - dc_shell-t -f fsyn.tcl \ No newline at end of file + dc_shell-t -f fsyn.tcl 2>&1 | tee vortex_syn.log \ No newline at end of file diff --git a/syn/fsyn.tcl b/syn/fsyn.tcl index 882a297b..fc4f1797 100644 --- a/syn/fsyn.tcl +++ b/syn/fsyn.tcl @@ -4,6 +4,8 @@ set symbol_library {} set target_library [concat NanGate_15nm_OCL.db] set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v \ ] +# set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v \ +# ] set top_level Vortex analyze -format sverilog $verilog_files diff --git a/syn/vortex_syn.log b/syn/vortex_syn.log new file mode 100644 index 00000000..45276130 --- /dev/null +++ b/syn/vortex_syn.log @@ -0,0 +1,2531 @@ + + Design Compiler Graphical + DC Ultra (TM) + DFTMAX (TM) + Power Compiler (TM) + DesignWare (R) + DC Expert (TM) + Design Vision (TM) + HDL Compiler (TM) + VHDL Compiler (TM) + DFT Compiler + Library Compiler (TM) + Design Compiler(R) + + Version J-2014.09-SP3 for RHEL64 -- Jan 19, 2015 + Copyright (c) 1988-2015 Synopsys, Inc. + +This software and the associated documentation are confidential and +proprietary to Synopsys, Inc. Your use or disclosure of this software +is subject to the terms and conditions of a written license agreement +between you, or your company, and Synopsys, Inc. + +Initializing... +set search_path [concat ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache] +../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache +set link_library [concat NanGate_15nm_OCL.db] +NanGate_15nm_OCL.db +set symbol_library {} +set target_library [concat NanGate_15nm_OCL.db] +NanGate_15nm_OCL.db +set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v ] +VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v +# set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v # ] +set top_level Vortex +Vortex +analyze -format sverilog $verilog_files +Running PRESTO HDLC +Searching for ../rtl/VX_countones.v +Searching for ../rtl/VX_priority_encoder_w_mask.v +Searching for ../rtl/VX_dram_req_rsp_inter.v +Searching for ../rtl/interfaces/VX_dram_req_rsp_inter.v +Searching for ../rtl/cache_set.v +Searching for ../rtl/interfaces/cache_set.v +Searching for ../rtl/pipe_regs/cache_set.v +Searching for ../rtl/shared_memory/cache_set.v +Searching for ../rtl/cache/cache_set.v +Searching for ../rtl/VX_Cache_Bank.v +Searching for ../rtl/interfaces/VX_Cache_Bank.v +Searching for ../rtl/pipe_regs/VX_Cache_Bank.v +Searching for ../rtl/shared_memory/VX_Cache_Bank.v +Searching for ../rtl/cache/VX_Cache_Bank.v +Searching for ../rtl/VX_Cache_Block_DM.v +Searching for ../rtl/interfaces/VX_Cache_Block_DM.v +Searching for ../rtl/pipe_regs/VX_Cache_Block_DM.v +Searching for ../rtl/shared_memory/VX_Cache_Block_DM.v +Searching for ../rtl/cache/VX_Cache_Block_DM.v +Searching for ../rtl/VX_cache_data.v +Searching for ../rtl/interfaces/VX_cache_data.v +Searching for ../rtl/pipe_regs/VX_cache_data.v +Searching for ../rtl/shared_memory/VX_cache_data.v +Searching for ../rtl/cache/VX_cache_data.v +Searching for ../rtl/VX_d_cache.v +Searching for ../rtl/interfaces/VX_d_cache.v +Searching for ../rtl/pipe_regs/VX_d_cache.v +Searching for ../rtl/shared_memory/VX_d_cache.v +Searching for ../rtl/cache/VX_d_cache.v +Searching for ../rtl/VX_bank_valids.v +Searching for ../rtl/interfaces/VX_bank_valids.v +Searching for ../rtl/pipe_regs/VX_bank_valids.v +Searching for ../rtl/shared_memory/VX_bank_valids.v +Searching for ../rtl/VX_priority_encoder_sm.v +Searching for ../rtl/interfaces/VX_priority_encoder_sm.v +Searching for ../rtl/pipe_regs/VX_priority_encoder_sm.v +Searching for ../rtl/shared_memory/VX_priority_encoder_sm.v +Searching for ../rtl/VX_shared_memory.v +Searching for ../rtl/interfaces/VX_shared_memory.v +Searching for ../rtl/pipe_regs/VX_shared_memory.v +Searching for ../rtl/shared_memory/VX_shared_memory.v +Searching for ../rtl/VX_shared_memory_block.v +Searching for ../rtl/interfaces/VX_shared_memory_block.v +Searching for ../rtl/pipe_regs/VX_shared_memory_block.v +Searching for ../rtl/shared_memory/VX_shared_memory_block.v +Searching for ../rtl/VX_dmem_controller.v +Searching for ../rtl/VX_generic_priority_encoder.v +Searching for ../rtl/VX_generic_stack.v +Searching for ../rtl/VX_join_inter.v +Searching for ../rtl/interfaces/VX_join_inter.v +Searching for ../rtl/VX_csr_wrapper.v +Searching for ../rtl/VX_csr_req_inter.v +Searching for ../rtl/interfaces/VX_csr_req_inter.v +Searching for ../rtl/VX_csr_wb_inter.v +Searching for ../rtl/interfaces/VX_csr_wb_inter.v +Searching for ../rtl/VX_gpgpu_inst.v +Searching for ../rtl/VX_gpu_inst_req_inter.v +Searching for ../rtl/interfaces/VX_gpu_inst_req_inter.v +Searching for ../rtl/VX_wstall_inter.v +Searching for ../rtl/interfaces/VX_wstall_inter.v +Searching for ../rtl/VX_inst_exec_wb_inter.v +Searching for ../rtl/interfaces/VX_inst_exec_wb_inter.v +Searching for ../rtl/VX_lsu.v +Searching for ../rtl/VX_execute_unit.v +Searching for ../rtl/VX_lsu_addr_gen.v +Searching for ../rtl/VX_inst_multiplex.v +Searching for ../rtl/VX_exec_unit_req_inter.v +Searching for ../rtl/interfaces/VX_exec_unit_req_inter.v +Searching for ../rtl/VX_lsu_req_inter.v +Searching for ../rtl/interfaces/VX_lsu_req_inter.v +Searching for ../rtl/VX_alu.v +Searching for ../rtl/VX_back_end.v +Searching for ../rtl/VX_gpr_stage.v +Searching for ../rtl/VX_gpr_data_inter.v +Searching for ../rtl/interfaces/VX_gpr_data_inter.v +Searching for ../rtl/VX_csr_handler.v +Searching for ../rtl/VX_decode.v +Searching for ../rtl/VX_define.v +Searching for ../rtl/VX_scheduler.v +Searching for ../rtl/VX_fetch.v +Searching for ../rtl/VX_front_end.v +Searching for ../rtl/VX_generic_register.v +Searching for ../rtl/VX_gpr.v +Searching for ../rtl/VX_gpr_wrapper.v +Searching for ../rtl/VX_one_counter.v +Searching for ../rtl/VX_priority_encoder.v +Searching for ../rtl/VX_warp_scheduler.v +Searching for ../rtl/VX_writeback.v +Searching for ../rtl/byte_enabled_simple_dual_port_ram.v +Searching for ../rtl/VX_branch_response_inter.v +Searching for ../rtl/interfaces/VX_branch_response_inter.v +Searching for ../rtl/VX_dcache_request_inter.v +Searching for ../rtl/interfaces/VX_dcache_request_inter.v +Searching for ../rtl/VX_dcache_response_inter.v +Searching for ../rtl/interfaces/VX_dcache_response_inter.v +Searching for ../rtl/VX_frE_to_bckE_req_inter.v +Searching for ../rtl/interfaces/VX_frE_to_bckE_req_inter.v +Searching for ../rtl/VX_gpr_clone_inter.v +Searching for ../rtl/interfaces/VX_gpr_clone_inter.v +Searching for ../rtl/VX_gpr_jal_inter.v +Searching for ../rtl/interfaces/VX_gpr_jal_inter.v +Searching for ../rtl/VX_gpr_read_inter.v +Searching for ../rtl/interfaces/VX_gpr_read_inter.v +Searching for ../rtl/VX_gpr_wspawn_inter.v +Searching for ../rtl/interfaces/VX_gpr_wspawn_inter.v +Searching for ../rtl/VX_icache_request_inter.v +Searching for ../rtl/interfaces/VX_icache_request_inter.v +Searching for ../rtl/VX_icache_response_inter.v +Searching for ../rtl/interfaces/VX_icache_response_inter.v +Searching for ../rtl/VX_inst_mem_wb_inter.v +Searching for ../rtl/interfaces/VX_inst_mem_wb_inter.v +Searching for ../rtl/VX_inst_meta_inter.v +Searching for ../rtl/interfaces/VX_inst_meta_inter.v +Searching for ../rtl/VX_jal_response_inter.v +Searching for ../rtl/interfaces/VX_jal_response_inter.v +Searching for ../rtl/VX_mem_req_inter.v +Searching for ../rtl/interfaces/VX_mem_req_inter.v +Searching for ../rtl/VX_mw_wb_inter.v +Searching for ../rtl/interfaces/VX_mw_wb_inter.v +Searching for ../rtl/VX_warp_ctl_inter.v +Searching for ../rtl/interfaces/VX_warp_ctl_inter.v +Searching for ../rtl/VX_wb_inter.v +Searching for ../rtl/interfaces/VX_wb_inter.v +Searching for ../rtl/VX_d_e_reg.v +Searching for ../rtl/interfaces/VX_d_e_reg.v +Searching for ../rtl/pipe_regs/VX_d_e_reg.v +Searching for ../rtl/VX_f_d_reg.v +Searching for ../rtl/interfaces/VX_f_d_reg.v +Searching for ../rtl/pipe_regs/VX_f_d_reg.v +Searching for ../rtl/Vortex.v +Compiling source file ../rtl/VX_countones.v +Compiling source file ../rtl/VX_priority_encoder_w_mask.v +Compiling source file ../rtl/interfaces/VX_dram_req_rsp_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_dram_req_rsp_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/cache/cache_set.v +Compiling source file ../rtl/cache/VX_Cache_Bank.v +Opening include file ../rtl/interfaces/../VX_define.v +Compiling source file ../rtl/cache/VX_Cache_Block_DM.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/cache/VX_cache_data.v +Opening include file ../rtl/interfaces/../VX_define.v +Compiling source file ../rtl/cache/VX_d_cache.v +Opening include file ../rtl/interfaces/../VX_define.v +Warning: ../rtl/cache/VX_d_cache.v:50: Parameter keyword used in local parameter declaration. (VER-329) +Compiling source file ../rtl/shared_memory/VX_bank_valids.v +Opening include file ../rtl/interfaces/../VX_define.v +Compiling source file ../rtl/shared_memory/VX_priority_encoder_sm.v +Opening include file ../rtl/interfaces/../VX_define.v +Compiling source file ../rtl/shared_memory/VX_shared_memory.v +Opening include file ../rtl/interfaces/../VX_define.v +Compiling source file ../rtl/shared_memory/VX_shared_memory_block.v +Compiling source file ../rtl/VX_dmem_controller.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_generic_priority_encoder.v +Compiling source file ../rtl/VX_generic_stack.v +Compiling source file ../rtl/interfaces/VX_join_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_join_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/VX_csr_wrapper.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/interfaces/VX_csr_req_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_csr_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_csr_wb_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_csr_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/VX_gpgpu_inst.v +Opening include file ../rtl//VX_define.v +Warning: ../rtl/VX_gpgpu_inst.v:66: the undeclared symbol 'num_valids' assumed to have the default net type, which is 'wire'. (VER-936) +Compiling source file ../rtl/interfaces/VX_gpu_inst_req_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_gpu_inst_req_inter.v:7: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_wstall_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_wstall_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_inst_exec_wb_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_inst_exec_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/VX_lsu.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_execute_unit.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_lsu_addr_gen.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_inst_multiplex.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/interfaces/VX_exec_unit_req_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_exec_unit_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_lsu_req_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_lsu_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/VX_alu.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_back_end.v +Compiling source file ../rtl/VX_gpr_stage.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/interfaces/VX_gpr_data_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_gpr_data_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/VX_csr_handler.v +Compiling source file ../rtl/VX_decode.v +Opening include file ../rtl//VX_define.v +Warning: ../rtl/VX_csr_handler.v:41: The statements in initial blocks are ignored. (VER-281) +Compiling source file ../rtl/VX_define.v +Compiling source file ../rtl/VX_scheduler.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_fetch.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_front_end.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_generic_register.v +Compiling source file ../rtl/VX_gpr.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_gpr_wrapper.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_one_counter.v +Compiling source file ../rtl/VX_priority_encoder.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_warp_scheduler.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_writeback.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/byte_enabled_simple_dual_port_ram.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/interfaces/VX_branch_response_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_branch_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_dcache_request_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_dcache_request_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_dcache_response_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_dcache_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_frE_to_bckE_req_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_frE_to_bckE_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_gpr_clone_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_gpr_clone_inter.v:9: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_gpr_jal_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_gpr_jal_inter.v:7: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_gpr_read_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_gpr_read_inter.v:7: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_gpr_wspawn_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_gpr_wspawn_inter.v:7: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_icache_request_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_icache_request_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_icache_response_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_icache_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_inst_mem_wb_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_inst_mem_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_inst_meta_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_inst_meta_inter.v:7: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_jal_response_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_jal_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_mem_req_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_mem_req_inter.v:7: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_mw_wb_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_mw_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_warp_ctl_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_warp_ctl_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_wb_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/pipe_regs/VX_d_e_reg.v +Opening include file ../rtl/interfaces/../VX_define.v +Compiling source file ../rtl/pipe_regs/VX_f_d_reg.v +Opening include file ../rtl/interfaces/../VX_define.v +Compiling source file ../rtl/Vortex.v +Opening include file ../rtl/interfaces/../VX_define.v +Presto compilation completed successfully. +Warning: Can't read link_library file 'NanGate_15nm_OCL.db'. (UID-3) +1 +elaborate Vortex +Loading db file '/tools/synopsys/synthesis/j201409sp3/libraries/syn/gtech.db' +Loading db file '/tools/synopsys/synthesis/j201409sp3/libraries/syn/standard.sldb' + Loading link library 'gtech' +Warning: Can't read link_library file 'NanGate_15nm_OCL.db'. (UID-3) +Running PRESTO HDLC +Presto compilation completed successfully. +Elaborated 1 design. +Current design is now 'Vortex'. +Warning: Can't read link_library file 'NanGate_15nm_OCL.db'. (UID-3) +Information: Building the design 'VX_front_end' instantiated from design 'Vortex' with + the parameters "|((N%clk%)(N%reset%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%schedule_delay%)(N%icache_response_fe%I%WORK/VX_icache_response_inter%%)(N%icache_request_fe%I%WORK/VX_icache_request_inter%%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%)(N%fetch_ebreak%))". (HDL-193) +Presto compilation completed successfully. +Warning: Filename too long >255 chars. Renaming file: +'/nethome/felsabbagh3/research/Vortex/syn/VX_FRONT_END_I_VX_WARP_CTL_VX_WARP_CTL_INTER__I_ICACHE_RESPONSE_FE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_FE_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_VX_BCKE_REQ_VX_FRE_TO_BCKE_REQ_INTER__.mr' +to +'/nethome/felsabbagh3/research/Vortex/syn/VX_FRONT_END_I_VX_WARP_CTL_VX_WARP_CTL_INTER__I_ICACHE_RESPONSE_FE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_FE_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_35FE527370C98E3C09E2E6E2555D7EE6F02ECB4FA9775364_000.mr' +Information: Building the design 'VX_scheduler' instantiated from design 'Vortex' with + the parameters "|((N%clk%)(N%reset%)(N%memory_delay%)(N%gpr_stage_delay%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%schedule_delay%))". (HDL-193) + +Inferred memory devices in process + in routine VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__ line 46 in file + '../rtl/VX_scheduler.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| rename_table_reg | Flip-flop | 32 | N | N | Y | N | N | N | N | +=============================================================================== +Statistics for MUX_OPs +===================================================================================================================================== +| block name/line | Inputs | Outputs | # sel inputs | MB | +===================================================================================================================================== +| VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__/28 | 32 | 1 | 5 | N | +| VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__/29 | 32 | 1 | 5 | N | +===================================================================================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_back_end' instantiated from design 'Vortex' with + the parameters "|((N%clk%)(N%reset%)(N%schedule_delay%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%)(N%VX_dcache_rsp%I%WORK/VX_dcache_response_inter%%)(N%VX_dcache_req%I%WORK/VX_dcache_request_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%out_mem_delay%)(N%gpr_stage_delay%))". (HDL-193) +Presto compilation completed successfully. +Warning: Filename too long >255 chars. Renaming file: +'/nethome/felsabbagh3/research/Vortex/syn/VX_BACK_END_I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_VX_BCKE_REQ_VX_FRE_TO_BCKE_REQ_INTER__I_VX_WRITEBACK_INTER_VX_WB_INTER__I_VX_WARP_CTL_VX_WARP_CTL_INTER__I_VX_DCACHE_RSP_VX_DCACHE_RESPONSE_INTER__I_VX_DCACHE_REQ_VX_DCACHE_REQUEST_INTER__.mr' +to +'/nethome/felsabbagh3/research/Vortex/syn/VX_BACK_END_I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_VX_BCKE_REQ_VX_FRE_TO_BCKE_REQ_INTER__I_VX_WRITEBACK_INTER_VX_WB_INTER__I_VX_WARP_CTL_VX_WARP_CTL_INTER__I__B458045CB598257C352A6473E41AFB0017DAE536C3121AF6_000.mr' +Information: Building the design 'VX_dmem_controller' instantiated from design 'Vortex' with + the parameters "|((N%clk%)(N%reset%)(N%VX_dram_req_rsp%I%WORK/VX_dram_req_rsp_inter%%)(N%VX_dcache_req%I%WORK/VX_dcache_request_inter%%)(N%VX_dcache_rsp%I%WORK/VX_dcache_response_inter%%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_fetch' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with + the parameters "|((N%clk%)(N%reset%)(N%VX_wstall%I%WORK/VX_wstall_inter%%)(N%VX_join%I%WORK/VX_join_inter%%)(N%schedule_delay%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%icache_response%I%WORK/VX_icache_response_inter%%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%)(N%icache_request%I%WORK/VX_icache_request_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%)(N%out_ebreak%)(N%fe_inst_meta_fd%I%WORK/VX_inst_meta_inter%%))". (HDL-193) +Presto compilation completed successfully. +Warning: Filename too long >255 chars. Renaming file: +'/nethome/felsabbagh3/research/Vortex/syn/VX_FETCH_I_VX_WSTALL_VX_WSTALL_INTER__I_VX_JOIN_VX_JOIN_INTER__I_ICACHE_RESPONSE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_FE_INST_META_FD_VX_INST_META_INTER__I_VX_WARP_CTL_VX_WARP_CTL_INTER__.mr' +to +'/nethome/felsabbagh3/research/Vortex/syn/VX_FETCH_I_VX_WSTALL_VX_WSTALL_INTER__I_VX_JOIN_VX_JOIN_INTER__I_ICACHE_RESPONSE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RS_86A42238AAF2AFE24C53E826055B694A355B7E541802DCF6_000.mr' +Information: Building the design 'VX_f_d_reg' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with + the parameters "|((N%clk%)(N%reset%)(N%in_freeze%)(N%fe_inst_meta_fd%I%WORK/VX_inst_meta_inter%%)(N%fd_inst_meta_de%I%WORK/VX_inst_meta_inter%%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_decode' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with + the parameters "|((N%fd_inst_meta_de%I%WORK/VX_inst_meta_inter%%)(N%VX_frE_to_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_wstall%I%WORK/VX_wstall_inter%%)(N%VX_join%I%WORK/VX_join_inter%%))". (HDL-193) +Warning: ../rtl/VX_decode.v:152: signed to unsigned assignment occurs. (VER-318) +Warning: ../rtl/VX_decode.v:300: DEFAULT branch of CASE statement cannot be reached. (ELAB-311) +Warning: ../rtl/VX_decode.v:315: DEFAULT branch of CASE statement cannot be reached. (ELAB-311) + +Statistics for case statements in always block at line 159 in file + '../rtl/VX_decode.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 160 | auto/auto | +=============================================== + +Statistics for case statements in always block at line 190 in file + '../rtl/VX_decode.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 191 | auto/auto | +=============================================== + +Statistics for case statements in always block at line 244 in file + '../rtl/VX_decode.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 245 | auto/auto | +=============================================== + +Statistics for case statements in always block at line 258 in file + '../rtl/VX_decode.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 259 | auto/auto | +| 264 | auto/auto | +=============================================== + +Statistics for case statements in always block at line 298 in file + '../rtl/VX_decode.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 300 | auto/auto | +=============================================== + +Statistics for case statements in always block at line 313 in file + '../rtl/VX_decode.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 315 | auto/auto | +=============================================== + +Statistics for case statements in always block at line 330 in file + '../rtl/VX_decode.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 331 | auto/auto | +=============================================== +Presto compilation completed successfully. +Information: Building the design 'VX_d_e_reg' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with + the parameters "|((N%clk%)(N%reset%)(N%in_branch_stall%)(N%in_freeze%)(N%VX_frE_to_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_mw_wb_inter'. (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_mem_req_inter'. (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_gpr_stage' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with + the parameters "|((N%clk%)(N%reset%)(N%schedule_delay%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_exec_unit_req%I%WORK/VX_exec_unit_req_inter%%)(N%VX_lsu_req%I%WORK/VX_lsu_req_inter%%)(N%VX_gpu_inst_req%I%WORK/VX_gpu_inst_req_inter%%)(N%VX_csr_req%I%WORK/VX_csr_req_inter%%)(N%memory_delay%)(N%gpr_stage_delay%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_lsu' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with + the parameters "|((N%clk%)(N%reset%)(N%VX_lsu_req%I%WORK/VX_lsu_req_inter%%)(N%VX_mem_wb%I%WORK/VX_inst_mem_wb_inter%%)(N%VX_dcache_rsp%I%WORK/VX_dcache_response_inter%%)(N%VX_dcache_req%I%WORK/VX_dcache_request_inter%%)(N%out_delay%)(N%no_slot_mem%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_execute_unit' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with + the parameters "|((N%VX_exec_unit_req%I%WORK/VX_exec_unit_req_inter%%)(N%VX_inst_exec_wb%I%WORK/VX_inst_exec_wb_inter%%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%))". (HDL-193) +Warning: ../rtl/VX_execute_unit.v:107: signed to unsigned assignment occurs. (VER-318) +Warning: ../rtl/VX_execute_unit.v:114: signed to unsigned assignment occurs. (VER-318) + +Statistics for case statements in always block at line 74 in file + '../rtl/VX_execute_unit.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 76 | auto/auto | +=============================================== +Statistics for MUX_OPs +================================================================================================================================================================================================================================ +| block name/line | Inputs | Outputs | # sel inputs | MB | +================================================================================================================================================================================================================================ +| VX_execute_unit_I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__/71 | 4 | 32 | 2 | N | +================================================================================================================================================================================================================================ +Presto compilation completed successfully. +Information: Building the design 'VX_gpgpu_inst' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with + the parameters "|((N%VX_gpu_inst_req%I%WORK/VX_gpu_inst_req_inter%%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_csr_wrapper' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with + the parameters "|((N%VX_csr_req%I%WORK/VX_csr_req_inter%%)(N%VX_csr_wb%I%WORK/VX_csr_wb_inter%%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_writeback' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with + the parameters "|((N%VX_mem_wb%I%WORK/VX_inst_mem_wb_inter%%)(N%VX_inst_exec_wb%I%WORK/VX_inst_exec_wb_inter%%)(N%VX_csr_wb%I%WORK/VX_csr_wb_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%no_slot_mem%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_shared_memory' instantiated from design 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__' with + the parameters "NB=7,BITS_PER_BANK=3". (HDL-193) + +Inferred memory devices in process + in routine VX_shared_memory_NB7_BITS_PER_BANK3 line 86 in file + '../rtl/shared_memory/VX_shared_memory.v'. +=========================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=========================================================================== +| temp_out_data_reg | Latch | 5 | Y | N | N | N | - | - | - | +| temp_out_data_reg | Latch | 9 | Y | N | N | N | - | - | - | +| temp_out_data_reg | Latch | 9 | Y | N | N | N | - | - | - | +| temp_out_data_reg | Latch | 9 | Y | N | N | N | - | - | - | +| temp_out_data_reg | Latch | 5 | Y | N | N | N | - | - | - | +| temp_out_data_reg | Latch | 9 | Y | N | N | N | - | - | - | +| temp_out_data_reg | Latch | 9 | Y | N | N | N | - | - | - | +| temp_out_data_reg | Latch | 9 | Y | N | N | N | - | - | - | +| temp_out_data_reg | Latch | 5 | Y | N | N | N | - | - | - | +| temp_out_data_reg | Latch | 9 | Y | N | N | N | - | - | - | +| temp_out_data_reg | Latch | 9 | Y | N | N | N | - | - | - | +| temp_out_data_reg | Latch | 9 | Y | N | N | N | - | - | - | +| temp_out_data_reg | Latch | 5 | Y | N | N | N | - | - | - | +| temp_out_data_reg | Latch | 9 | Y | N | N | N | - | - | - | +| temp_out_data_reg | Latch | 9 | Y | N | N | N | - | - | - | +| temp_out_data_reg | Latch | 9 | Y | N | N | N | - | - | - | +| shm_write_reg | Latch | 1 | N | N | N | N | - | - | - | +| temp_out_valid_reg | Latch | 4 | N | N | N | N | - | - | - | +=========================================================================== +Statistics for MUX_OPs +================================================================================== +| block name/line | Inputs | Outputs | # sel inputs | MB | +================================================================================== +| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 | N | +| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 | N | +| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 | N | +| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 | N | +| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 | N | +| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 | N | +| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 | N | +| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 | N | +================================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_d_cache' instantiated from design 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__' with + the parameters "CACHE_SIZE=4096,CACHE_WAYS=1,CACHE_BLOCK=128,CACHE_BANKS=8,NUM_REQ=4". (HDL-193) +Warning: ../rtl/cache/VX_d_cache.v:201: signed to unsigned assignment occurs. (VER-318) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][31] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][30] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][29] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][28] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][27] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][26] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][25] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][24] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][23] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][22] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][21] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][20] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][19] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][18] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][17] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][16] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][15] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][14] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][13] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][12] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][11] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][10] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][9] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][8] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][7] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][6] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][5] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][4] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][3] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][2] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][1] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][0] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][31] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][30] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][29] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][28] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][27] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][26] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][25] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][24] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][23] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][22] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][21] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][20] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][19] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][18] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][17] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][16] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][15] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][14] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][13] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][12] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][11] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][10] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][9] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][8] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][7] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][6] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][5] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][4] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][3] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][2] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][1] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][0] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][31] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][30] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][29] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][28] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][27] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][26] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][25] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][24] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][23] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][22] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][21] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][20] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][19] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][18] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][17] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][16] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][15] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][14] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][13] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][12] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][11] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][10] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][9] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][8] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][7] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][6] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][5] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][4] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][3] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][2] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][1] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][0] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][31] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][30] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][29] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][28] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][27] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][26] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][25] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][24] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][23] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][22] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][21] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][20] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][19] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][18] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][17] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][16] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][15] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][14] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][13] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][12] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][11] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][10] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][9] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][8] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][7] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][6] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][5] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][4] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][3] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][2] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][1] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][0] or a directly connected net may be driven by more than one process or block. (ELAB-405) + +Inferred memory devices in process + in routine VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4 line 149 in file + '../rtl/cache/VX_d_cache.v'. +================================================================================ +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +================================================================================ +| new_final_data_read_reg | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg2 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg2 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg2 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg2 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg3 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg3 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg3 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg3 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg4 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg4 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg4 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg4 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg5 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg5 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg5 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg5 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg6 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg6 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg6 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg6 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg7 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg7 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg7 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg7 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg8 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg8 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg8 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg8 | Latch | 32 | Y | N | N | N | - | - | - | +================================================================================ + +Inferred memory devices in process + in routine VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4 line 212 in file + '../rtl/cache/VX_d_cache.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| evict_addr_reg | Flip-flop | 29 | Y | N | Y | N | N | N | N | +| final_data_read_reg | Flip-flop | 128 | Y | N | Y | N | N | N | N | +| state_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | +| stored_valid_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | +| miss_addr_reg | Flip-flop | 29 | Y | N | Y | N | N | N | N | +=============================================================================== +Statistics for MUX_OPs +========================================================================================================================= +| block name/line | Inputs | Outputs | # sel inputs | MB | +========================================================================================================================= +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/233 | 8 | 2 | 3 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/233 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/234 | 8 | 29 | 3 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +========================================================================================================================= +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][31]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][30]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][29]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][28]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][27]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][26]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][25]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][24]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][23]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][22]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][21]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][20]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][19]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][18]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][17]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][16]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][15]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][14]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][13]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +*** Presto compilation terminated with 19 errors. *** +Information: Building the design 'VX_warp_scheduler'. (HDL-193) + +Inferred memory devices in process + in routine VX_warp_scheduler line 113 in file + '../rtl/VX_warp_scheduler.v'. +================================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +================================================================================== +| thread_masks_reg | Flip-flop | 3 | Y | N | Y | N | N | N | N | +| thread_masks_reg | Flip-flop | 3 | Y | N | Y | N | N | N | N | +| thread_masks_reg | Flip-flop | 3 | Y | N | Y | N | N | N | N | +| thread_masks_reg | Flip-flop | 3 | Y | N | Y | N | N | N | N | +| thread_masks_reg | Flip-flop | 3 | Y | N | Y | N | N | N | N | +| thread_masks_reg | Flip-flop | 3 | Y | N | Y | N | N | N | N | +| thread_masks_reg | Flip-flop | 3 | Y | N | Y | N | N | N | N | +| thread_masks_reg | Flip-flop | 3 | Y | N | Y | N | N | N | N | +| thread_masks_reg | Flip-flop | 8 | N | N | N | Y | N | N | N | +| warp_stalled_reg | Flip-flop | 8 | N | N | Y | N | N | N | N | +| barrier_stall_mask_reg | Flip-flop | 32 | N | N | Y | N | N | N | N | +| use_wsapwn_pc_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| use_wsapwn_reg | Flip-flop | 8 | N | N | Y | N | N | N | N | +| warp_pcs_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| warp_pcs_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| warp_pcs_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| warp_pcs_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| warp_pcs_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| warp_pcs_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| warp_pcs_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| warp_pcs_reg | Flip-flop | 3 | Y | N | Y | N | N | N | N | +| warp_pcs_reg | Flip-flop | 29 | Y | N | N | Y | N | N | N | +| warp_active_reg | Flip-flop | 7 | N | N | Y | N | N | N | N | +| warp_active_reg | Flip-flop | 1 | N | N | N | Y | N | N | N | +| visible_active_reg | Flip-flop | 7 | N | N | Y | N | N | N | N | +| visible_active_reg | Flip-flop | 1 | N | N | N | Y | N | N | N | +================================================================================== +Statistics for MUX_OPs +================================================================ +| block name/line | Inputs | Outputs | # sel inputs | MB | +================================================================ +| VX_warp_scheduler/215 | 4 | 8 | 2 | N | +| VX_warp_scheduler/233 | 8 | 4 | 3 | N | +| VX_warp_scheduler/237 | 8 | 37 | 3 | N | +| VX_warp_scheduler/266 | 8 | 3 | 3 | N | +| VX_warp_scheduler/273 | 8 | 32 | 3 | N | +| VX_warp_scheduler/274 | 8 | 4 | 3 | N | +================================================================ +Presto compilation completed successfully. +Information: Building the design 'VX_generic_register' instantiated from design 'VX_f_d_reg_I_fe_inst_meta_fd_VX_inst_meta_inter__I_fd_inst_meta_de_VX_inst_meta_inter__' with + the parameters "N=71". (HDL-193) + +Inferred memory devices in process + in routine VX_generic_register_N71 line 21 in file + '../rtl/VX_generic_register.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| value_reg | Flip-flop | 71 | Y | N | Y | N | N | N | N | +=============================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_generic_register' instantiated from design 'VX_d_e_reg_I_VX_frE_to_bckE_req_VX_frE_to_bckE_req_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with + the parameters "N=240". (HDL-193) + +Inferred memory devices in process + in routine VX_generic_register_N240 line 21 in file + '../rtl/VX_generic_register.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| value_reg | Flip-flop | 240 | Y | N | Y | N | N | N | N | +=============================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_gpr_wrapper' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with + the parameters "|((N%clk%)(N%reset%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%VX_gpr_read%I%WORK/VX_gpr_read_inter%%)(N%VX_gpr_jal%I%WORK/VX_gpr_jal_inter%%)(N%out_a_reg_data%)(N%out_b_reg_data%))". (HDL-193) +Statistics for MUX_OPs +=============================================================================================================================================================== +| block name/line | Inputs | Outputs | # sel inputs | MB | +=============================================================================================================================================================== +| VX_gpr_wrapper_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_gpr_jal_VX_gpr_jal_inter__/25 | 8 | 256 | 3 | N | +=============================================================================================================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_inst_multiplex' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with + the parameters "|((N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_gpr_data%I%WORK/VX_gpr_data_inter%%)(N%VX_exec_unit_req%I%WORK/VX_exec_unit_req_inter%%)(N%VX_lsu_req%I%WORK/VX_lsu_req_inter%%)(N%VX_gpu_inst_req%I%WORK/VX_gpu_inst_req_inter%%)(N%VX_csr_req%I%WORK/VX_csr_req_inter%%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with + the parameters "N=308". (HDL-193) + +Inferred memory devices in process + in routine VX_generic_register_N308 line 21 in file + '../rtl/VX_generic_register.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| value_reg | Flip-flop | 308 | Y | N | Y | N | N | N | N | +=============================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with + the parameters "N=487". (HDL-193) + +Inferred memory devices in process + in routine VX_generic_register_N487 line 21 in file + '../rtl/VX_generic_register.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| value_reg | Flip-flop | 487 | Y | N | Y | N | N | N | N | +=============================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with + the parameters "N=203". (HDL-193) + +Inferred memory devices in process + in routine VX_generic_register_N203 line 21 in file + '../rtl/VX_generic_register.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| value_reg | Flip-flop | 203 | Y | N | Y | N | N | N | N | +=============================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with + the parameters "N=60". (HDL-193) + +Inferred memory devices in process + in routine VX_generic_register_N60 line 21 in file + '../rtl/VX_generic_register.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| value_reg | Flip-flop | 60 | Y | N | Y | N | N | N | N | +=============================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_lsu_addr_gen'. (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_alu'. (HDL-193) +Warning: ../rtl/VX_alu.v:40: signed to unsigned assignment occurs. (VER-318) +Warning: ../rtl/VX_alu.v:49: signed to unsigned assignment occurs. (VER-318) +Warning: ../rtl/VX_alu.v:50: signed to unsigned assignment occurs. (VER-318) +Warning: ../rtl/VX_alu.v:56: signed to unsigned assignment occurs. (VER-318) +Warning: ../rtl/VX_alu.v:61: signed to unsigned assignment occurs. (VER-318) +Warning: ../rtl/VX_alu.v:66: signed to unsigned conversion occurs. (VER-318) +Warning: ../rtl/VX_alu.v:68: signed to unsigned conversion occurs. (VER-318) + +Statistics for case statements in always block at line 47 in file + '../rtl/VX_alu.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 48 | auto/auto | +=============================================== +Presto compilation completed successfully. +Information: Building the design 'VX_generic_priority_encoder' instantiated from design 'VX_execute_unit_I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__' with + the parameters "N=4". (HDL-193) +Warning: ../rtl/VX_generic_priority_encoder.v:17: signed to unsigned part selection occurs. (VER-318) +Presto compilation completed successfully. +Information: Building the design 'VX_countones' instantiated from design 'VX_gpgpu_inst_I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_warp_ctl_VX_warp_ctl_inter__' with + the parameters "N=4". (HDL-193) +Presto compilation completed successfully. +Error: Width mismatch on port 'count' of reference to 'VX_countones' in 'VX_gpgpu_inst_I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_warp_ctl_VX_warp_ctl_inter__'. (LINK-3) +Error: Unable to match ports of cell vx_back_end/VX_gpgpu_inst/valids_counter ('VX_countones') to 'VX_countones_N4'. (LINK-25) +Information: Building the design 'VX_priority_encoder_sm' instantiated from design 'VX_shared_memory_NB7_BITS_PER_BANK3' with + the parameters "NB=7,BITS_PER_BANK=3". (HDL-193) + +Inferred memory devices in process + in routine VX_priority_encoder_sm_NB7_BITS_PER_BANK3 line 104 in file + '../rtl/shared_memory/VX_priority_encoder_sm.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| left_requests_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | +=============================================================================== +Statistics for MUX_OPs +======================================================================================= +| block name/line | Inputs | Outputs | # sel inputs | MB | +======================================================================================= +| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 | N | +| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 | N | +| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 | N | +| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 | N | +| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 | N | +| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 | N | +| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 | N | +| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 | N | +======================================================================================= +Presto compilation completed successfully. +Information: Building the design 'VX_shared_memory_block'. (HDL-193) + +Inferred memory devices in process + in routine VX_shared_memory_block line 20 in file + '../rtl/shared_memory/VX_shared_memory_block.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| shared_memory_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +=============================================================================== +Statistics for MUX_OPs +==================================================================== +| block name/line | Inputs | Outputs | # sel inputs | MB | +==================================================================== +| VX_shared_memory_block/35 | 128 | 128 | 7 | N | +==================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_countones' instantiated from design 'VX_warp_scheduler' with + the parameters "N=8". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_generic_stack' instantiated from design 'VX_warp_scheduler' with + the parameters "WIDTH=37,DEPTH=2". (HDL-193) + +Inferred memory devices in process + in routine VX_generic_stack_WIDTH37_DEPTH2 line 21 in file + '../rtl/VX_generic_stack.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| stack_reg | Flip-flop | 37 | Y | N | N | N | N | N | N | +| stack_reg | Flip-flop | 37 | Y | N | N | N | N | N | N | +| stack_reg | Flip-flop | 37 | Y | N | N | N | N | N | N | +| stack_reg | Flip-flop | 37 | Y | N | N | N | N | N | N | +| ptr_reg | Flip-flop | 2 | Y | N | N | N | N | N | N | +=============================================================================== +Statistics for MUX_OPs +============================================================================= +| block name/line | Inputs | Outputs | # sel inputs | MB | +============================================================================= +| VX_generic_stack_WIDTH37_DEPTH2/36 | 4 | 37 | 2 | N | +============================================================================= +Presto compilation completed successfully. +Information: Building the design 'VX_priority_encoder'. (HDL-193) +Warning: ../rtl/VX_priority_encoder.v:15: signed to unsigned part selection occurs. (VER-318) +Presto compilation completed successfully. +Information: Building the design 'VX_gpr' instantiated from design 'VX_gpr_wrapper_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_gpr_jal_VX_gpr_jal_inter__' with + the parameters "|((N%clk%)(N%reset%)(N%valid_write_request%)(N%VX_gpr_read%I%WORK/VX_gpr_read_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%out_a_reg_data%)(N%out_b_reg_data%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_bank_valids' instantiated from design 'VX_priority_encoder_sm_NB7_BITS_PER_BANK3' with + the parameters "NB=7,BITS_PER_BANK=3". (HDL-193) +Warning: ../rtl/shared_memory/VX_bank_valids.v:21: signed to unsigned part selection occurs. (VER-318) +Warning: ../rtl/shared_memory/VX_bank_valids.v:21: signed to unsigned part selection occurs. (VER-318) +Warning: ../rtl/shared_memory/VX_bank_valids.v:21: signed to unsigned part selection occurs. (VER-318) +Warning: ../rtl/shared_memory/VX_bank_valids.v:21: signed to unsigned part selection occurs. (VER-318) +Presto compilation completed successfully. +Information: Building the design 'byte_enabled_simple_dual_port_ram'. (HDL-193) + +Inferred memory devices in process + in routine byte_enabled_simple_dual_port_ram line 26 in file + '../rtl/byte_enabled_simple_dual_port_ram.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| GPR_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +=============================================================================== +Statistics for MUX_OPs +=============================================================================== +| block name/line | Inputs | Outputs | # sel inputs | MB | +=============================================================================== +| byte_enabled_simple_dual_port_ram/47 | 32 | 128 | 5 | N | +| byte_enabled_simple_dual_port_ram/48 | 32 | 128 | 5 | N | +=============================================================================== +Presto compilation completed successfully. +Warning: Design 'Vortex' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341) +1 +link +Warning: Can't read link_library file 'NanGate_15nm_OCL.db'. (UID-3) + + Linking design 'Vortex' + Using the following designs and libraries: + -------------------------------------------------------------------------- + +Information: Building the design 'VX_d_cache' instantiated from design 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__' with + the parameters "CACHE_SIZE=4096,CACHE_WAYS=1,CACHE_BLOCK=128,CACHE_BANKS=8,NUM_REQ=4". (HDL-193) +Warning: ../rtl/cache/VX_d_cache.v:201: signed to unsigned assignment occurs. (VER-318) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][31] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][30] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][29] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][28] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][27] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][26] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][25] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][24] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][23] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][22] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][21] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][20] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][19] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][18] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][17] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][16] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][15] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][14] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][13] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][12] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][11] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][10] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][9] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][8] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][7] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][6] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][5] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][4] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][3] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][2] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][1] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][0] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][31] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][30] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][29] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][28] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][27] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][26] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][25] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][24] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][23] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][22] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][21] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][20] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][19] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][18] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][17] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][16] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][15] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][14] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][13] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][12] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][11] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][10] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][9] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][8] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][7] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][6] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][5] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][4] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][3] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][2] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][1] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][0] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][31] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][30] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][29] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][28] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][27] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][26] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][25] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][24] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][23] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][22] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][21] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][20] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][19] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][18] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][17] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][16] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][15] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][14] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][13] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][12] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][11] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][10] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][9] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][8] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][7] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][6] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][5] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][4] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][3] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][2] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][1] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][0] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][31] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][30] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][29] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][28] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][27] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][26] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][25] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][24] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][23] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][22] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][21] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][20] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][19] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][18] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][17] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][16] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][15] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][14] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][13] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][12] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][11] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][10] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][9] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][8] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][7] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][6] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][5] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][4] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][3] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][2] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][1] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][0] or a directly connected net may be driven by more than one process or block. (ELAB-405) + +Inferred memory devices in process + in routine VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4 line 149 in file + '../rtl/cache/VX_d_cache.v'. +================================================================================ +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +================================================================================ +| new_final_data_read_reg | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg2 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg2 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg2 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg2 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg3 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg3 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg3 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg3 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg4 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg4 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg4 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg4 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg5 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg5 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg5 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg5 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg6 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg6 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg6 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg6 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg7 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg7 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg7 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg7 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg8 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg8 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg8 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg8 | Latch | 32 | Y | N | N | N | - | - | - | +================================================================================ + +Inferred memory devices in process + in routine VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4 line 212 in file + '../rtl/cache/VX_d_cache.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| evict_addr_reg | Flip-flop | 29 | Y | N | Y | N | N | N | N | +| final_data_read_reg | Flip-flop | 128 | Y | N | Y | N | N | N | N | +| state_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | +| stored_valid_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | +| miss_addr_reg | Flip-flop | 29 | Y | N | Y | N | N | N | N | +=============================================================================== +Statistics for MUX_OPs +========================================================================================================================= +| block name/line | Inputs | Outputs | # sel inputs | MB | +========================================================================================================================= +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/233 | 8 | 2 | 3 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/233 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/234 | 8 | 29 | 3 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +========================================================================================================================= +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][31]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][30]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][29]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][28]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][27]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][26]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][25]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][24]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][23]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][22]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][21]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][20]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][19]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][18]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][17]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][16]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][15]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][14]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][13]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +*** Presto compilation terminated with 19 errors. *** +Error: Width mismatch on port 'count' of reference to 'VX_countones' in 'VX_gpgpu_inst_I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_warp_ctl_VX_warp_ctl_inter__'. (LINK-3) +Error: Unable to match ports of cell vx_back_end/VX_gpgpu_inst/valids_counter ('VX_countones') to 'VX_countones_N4'. (LINK-25) +Warning: Unable to resolve reference 'VX_d_cache' in 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__'. (LINK-5) +0 +set clk_freq 100 +100 +set clk_period [expr 100.0 / $clk_freq / 1.0] +1.0 +create_clock [get_ports clk] -period $clk_period +Warning: Can't read link_library file 'NanGate_15nm_OCL.db'. (UID-3) +Information: Building the design 'VX_d_cache' instantiated from design 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__' with + the parameters "CACHE_SIZE=4096,CACHE_WAYS=1,CACHE_BLOCK=128,CACHE_BANKS=8,NUM_REQ=4". (HDL-193) +Warning: ../rtl/cache/VX_d_cache.v:201: signed to unsigned assignment occurs. (VER-318) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][31] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][30] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][29] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][28] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][27] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][26] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][25] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][24] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][23] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][22] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][21] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][20] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][19] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][18] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][17] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][16] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][15] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][14] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][13] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][12] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][11] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][10] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][9] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][8] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][7] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][6] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][5] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][4] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][3] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][2] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][1] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[3][0] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][31] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][30] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][29] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][28] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][27] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][26] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][25] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][24] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][23] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][22] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][21] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][20] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][19] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][18] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][17] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][16] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][15] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][14] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][13] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][12] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][11] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][10] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][9] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][8] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][7] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][6] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][5] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][4] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][3] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][2] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][1] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[2][0] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][31] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][30] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][29] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][28] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][27] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][26] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][25] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][24] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][23] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][22] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][21] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][20] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][19] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][18] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][17] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][16] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][15] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][14] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][13] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][12] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][11] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][10] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][9] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][8] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][7] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][6] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][5] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][4] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][3] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][2] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][1] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[1][0] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][31] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][30] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][29] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][28] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][27] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][26] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][25] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][24] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][23] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][22] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][21] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][20] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][19] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][18] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][17] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][16] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][15] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][14] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][13] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][12] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][11] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][10] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][9] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][8] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][7] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][6] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][5] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][4] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][3] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][2] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][1] or a directly connected net may be driven by more than one process or block. (ELAB-405) +Warning: ../rtl/cache/VX_d_cache.v:149: Net new_final_data_read[0][0] or a directly connected net may be driven by more than one process or block. (ELAB-405) + +Inferred memory devices in process + in routine VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4 line 149 in file + '../rtl/cache/VX_d_cache.v'. +================================================================================ +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +================================================================================ +| new_final_data_read_reg | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg2 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg2 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg2 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg2 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg3 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg3 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg3 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg3 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg4 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg4 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg4 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg4 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg5 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg5 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg5 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg5 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg6 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg6 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg6 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg6 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg7 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg7 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg7 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg7 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg8 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg8 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg8 | Latch | 32 | Y | N | N | N | - | - | - | +| new_final_data_read_reg8 | Latch | 32 | Y | N | N | N | - | - | - | +================================================================================ + +Inferred memory devices in process + in routine VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4 line 212 in file + '../rtl/cache/VX_d_cache.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| evict_addr_reg | Flip-flop | 29 | Y | N | Y | N | N | N | N | +| final_data_read_reg | Flip-flop | 128 | Y | N | Y | N | N | N | N | +| state_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | +| stored_valid_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | +| miss_addr_reg | Flip-flop | 29 | Y | N | Y | N | N | N | N | +=============================================================================== +Statistics for MUX_OPs +========================================================================================================================= +| block name/line | Inputs | Outputs | # sel inputs | MB | +========================================================================================================================= +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/233 | 8 | 2 | 3 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/233 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/234 | 8 | 29 | 3 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/246 | 4 | 29 | 2 | N | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/268 | 4 | 32 | 2 | N | +========================================================================================================================= +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][31]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][30]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][29]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][28]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][27]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][26]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][25]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][24]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][23]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][22]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][21]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][20]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][19]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][18]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][17]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][16]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][15]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][14]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +Error: ../rtl/cache/VX_d_cache.v:149: Net 'new_final_data_read[3][13]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) +*** Presto compilation terminated with 19 errors. *** +Error: Width mismatch on port 'count' of reference to 'VX_countones' in 'VX_gpgpu_inst_I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_warp_ctl_VX_warp_ctl_inter__'. (LINK-3) +Error: Unable to match ports of cell vx_back_end/VX_gpgpu_inst/valids_counter ('VX_countones') to 'VX_countones_N4'. (LINK-25) +Warning: Unable to resolve reference 'VX_d_cache' in 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__'. (LINK-5) +Warning: Design 'Vortex' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341) +1 +set_max_fanout 20 [get_ports clk] +1 +set_ideal_network [get_ports clk] +Warning: Design 'Vortex' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341) +1 +set_max_fanout 20 [get_ports reset] +1 +set_false_path -from [get_ports reset] +Warning: Design 'Vortex' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341) +1 +compile -no_map +Warning: Design 'Vortex' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341) +Error: Could not read the following target libraries: +NanGate_15nm_OCL.db + (UIO-3) +0 +exit + +Thank you...