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instruction decode refactoring fixing naming collision

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This commit is contained in:
Blaise Tine
2021-08-29 20:07:34 -07:00
parent 90b50277d0
commit a801a16062
32 changed files with 434 additions and 437 deletions
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4
hw/rtl/interfaces/VX_alu_req_if.v
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@@ -10,8 +10,8 @@ interface VX_alu_req_if ();
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [31:0] next_PC;
wire [`ALU_BITS-1:0] op_type;
wire [`MOD_BITS-1:0] op_mod;
wire [`INST_ALU_BITS-1:0] op_type;
wire [`INST_MOD_BITS-1:0] op_mod;
wire use_PC;
wire use_imm;
wire [31:0] imm;

2
hw/rtl/interfaces/VX_csr_req_if.v
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@@ -9,7 +9,7 @@ interface VX_csr_req_if ();
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`CSR_BITS-1:0] op_type;
wire [`INST_CSR_BITS-1:0] op_type;
wire [`CSR_ADDR_BITS-1:0] addr;
wire [31:0] rs1_data;
wire use_imm;

4
hw/rtl/interfaces/VX_decode_if.v
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@@ -10,8 +10,8 @@ interface VX_decode_if ();
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`EX_BITS-1:0] ex_type;
wire [`OP_BITS-1:0] op_type;
wire [`MOD_BITS-1:0] op_mod;
wire [`INST_OP_BITS-1:0] op_type;
wire [`INST_MOD_BITS-1:0] op_mod;
wire wb;
wire [`NR_BITS-1:0] rd;
wire [`NR_BITS-1:0] rs1;

4
hw/rtl/interfaces/VX_fpu_req_if.v
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@@ -9,8 +9,8 @@ interface VX_fpu_req_if ();
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`FPU_BITS-1:0] op_type;
wire [`MOD_BITS-1:0] op_mod;
wire [`INST_FPU_BITS-1:0] op_type;
wire [`INST_MOD_BITS-1:0] op_mod;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NUM_THREADS-1:0][31:0] rs3_data;

2
hw/rtl/interfaces/VX_fpu_to_csr_if.v
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@@ -10,7 +10,7 @@ interface VX_fpu_to_csr_if ();
fflags_t write_fflags;
wire [`NW_BITS-1:0] read_wid;
wire [`FRM_BITS-1:0] read_frm;
wire [`INST_FRM_BITS-1:0] read_frm;
endinterface

2
hw/rtl/interfaces/VX_gpu_req_if.v
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@@ -11,7 +11,7 @@ interface VX_gpu_req_if();
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [31:0] next_PC;
wire [`GPU_BITS-1:0] op_type;
wire [`INST_GPU_BITS-1:0] op_type;
wire [`NT_BITS-1:0] tid;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [31:0] rs2_data;

4
hw/rtl/interfaces/VX_ibuffer_if.v
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@@ -11,8 +11,8 @@ interface VX_ibuffer_if ();
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`EX_BITS-1:0] ex_type;
wire [`OP_BITS-1:0] op_type;
wire [`MOD_BITS-1:0] op_mod;
wire [`INST_OP_BITS-1:0] op_type;
wire [`INST_MOD_BITS-1:0] op_mod;
wire wb;
wire [`NR_BITS-1:0] rd;
wire [`NR_BITS-1:0] rs1;

2
hw/rtl/interfaces/VX_lsu_req_if.v
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@@ -9,7 +9,7 @@ interface VX_lsu_req_if ();
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`LSU_BITS-1:0] op_type;
wire [`INST_LSU_BITS-1:0] op_type;
wire is_fence;
wire [`NUM_THREADS-1:0][31:0] store_data;
wire [`NUM_THREADS-1:0][31:0] base_addr;