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instruction decode refactoring fixing naming collision

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This commit is contained in:
Blaise Tine
2021-08-29 20:07:34 -07:00
parent 90b50277d0
commit a801a16062
32 changed files with 434 additions and 437 deletions
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10
hw/rtl/fp_cores/VX_fp_cvt.v
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@@ -15,7 +15,7 @@ module VX_fp_cvt #(
input wire [TAGW-1:0] tag_in,
input wire [`FRM_BITS-1:0] frm,
input wire [`INST_FRM_BITS-1:0] frm,
input wire is_itof,
input wire is_signed,
@@ -101,7 +101,7 @@ module VX_fp_cvt #(
wire stall;
VX_pipe_register #(
.DATAW (1 + TAGW + 1 + `FRM_BITS + 1 + LANES * ($bits(fp_type_t) + 1 + INT_EXP_WIDTH + INT_MAN_WIDTH)),
.DATAW (1 + TAGW + 1 + `INST_FRM_BITS + 1 + LANES * ($bits(fp_type_t) + 1 + INT_EXP_WIDTH + INT_MAN_WIDTH)),
.RESETW (1)
) pipe_reg0 (
.clk (clk),
@@ -167,7 +167,7 @@ module VX_fp_cvt #(
wire [LANES-1:0][INT_EXP_WIDTH-1:0] input_exp_s1;
VX_pipe_register #(
.DATAW (1 + TAGW + 1 + `FRM_BITS + 1 + LANES * ($bits(fp_type_t) + 1 + 1 + INT_MAN_WIDTH + INT_EXP_WIDTH)),
.DATAW (1 + TAGW + 1 + `INST_FRM_BITS + 1 + LANES * ($bits(fp_type_t) + 1 + 1 + INT_MAN_WIDTH + INT_EXP_WIDTH)),
.RESETW (1)
) pipe_reg1 (
.clk (clk),
@@ -253,7 +253,7 @@ module VX_fp_cvt #(
wire [LANES-1:0] of_before_round_s2;
VX_pipe_register #(
.DATAW (1 + TAGW + 1 + 1 + `FRM_BITS + LANES * ($bits(fp_type_t) + 1 + 1 + (2*INT_MAN_WIDTH+1) + INT_EXP_WIDTH + 1)),
.DATAW (1 + TAGW + 1 + 1 + `INST_FRM_BITS + LANES * ($bits(fp_type_t) + 1 + 1 + (2*INT_MAN_WIDTH+1) + INT_EXP_WIDTH + 1)),
.RESETW (1)
) pipe_reg2 (
.clk (clk),
@@ -435,7 +435,7 @@ module VX_fp_cvt #(
assign stall = ~ready_out && valid_out;
VX_pipe_register #(
.DATAW (1 + TAGW + (LANES * 32) + (LANES * `FFG_BITS)),
.DATAW (1 + TAGW + (LANES * 32) + (LANES * `FFLAGS_BITS)),
.RESETW (1)
) pipe_reg4 (
.clk (clk),

2
hw/rtl/fp_cores/VX_fp_div.v
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@@ -16,7 +16,7 @@ module VX_fp_div #(
input wire [TAGW-1:0] tag_in,
input wire [`FRM_BITS-1:0] frm,
input wire [`INST_FRM_BITS-1:0] frm,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,

2
hw/rtl/fp_cores/VX_fp_fma.v
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@@ -16,7 +16,7 @@ module VX_fp_fma #(
input wire [TAGW-1:0] tag_in,
input wire [`FRM_BITS-1:0] frm,
input wire [`INST_FRM_BITS-1:0] frm,
input wire do_madd,
input wire do_sub,

30
hw/rtl/fp_cores/VX_fp_ncomp.v
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@@ -15,8 +15,8 @@ module VX_fp_ncomp #(
input wire [TAGW-1:0] tag_in,
input wire [`FPU_BITS-1:0] op_type,
input wire [`FRM_BITS-1:0] frm,
input wire [`INST_FPU_BITS-1:0] op_type,
input wire [`INST_FRM_BITS-1:0] frm,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
@@ -77,8 +77,8 @@ module VX_fp_ncomp #(
wire valid_in_s0;
wire [TAGW-1:0] tag_in_s0;
wire [`FPU_BITS-1:0] op_type_s0;
wire [`FRM_BITS-1:0] frm_s0;
wire [`INST_FPU_BITS-1:0] op_type_s0;
wire [`INST_FRM_BITS-1:0] frm_s0;
wire [LANES-1:0][31:0] dataa_s0, datab_s0;
wire [LANES-1:0] a_sign_s0, b_sign_s0;
wire [LANES-1:0][7:0] a_exponent_s0;
@@ -89,7 +89,7 @@ module VX_fp_ncomp #(
wire stall;
VX_pipe_register #(
.DATAW (1 + TAGW + `FPU_BITS + `FRM_BITS + LANES * (2 * 32 + 1 + 1 + 8 + 23 + 2 * $bits(fp_type_t) + 1 + 1)),
.DATAW (1 + TAGW + `INST_FPU_BITS + `INST_FRM_BITS + LANES * (2 * 32 + 1 + 1 + 8 + 23 + 2 * $bits(fp_type_t) + 1 + 1)),
.RESETW (1),
.DEPTH (0)
) pipe_reg0 (
@@ -164,7 +164,7 @@ module VX_fp_ncomp #(
for (genvar i = 0; i < LANES; i++) begin
always @(*) begin
case (frm_s0)
`FRM_RNE: begin // LE
`INST_FRM_RNE: begin // LE
fcmp_fflags[i] = 5'h0;
if (a_type_s0[i].is_nan || b_type_s0[i].is_nan) begin
fcmp_res[i] = 32'h0;
@@ -173,7 +173,7 @@ module VX_fp_ncomp #(
fcmp_res[i] = {31'h0, (a_smaller_s0[i] | ab_equal_s0[i])};
end
end
`FRM_RTZ: begin // LS
`INST_FRM_RTZ: begin // LS
fcmp_fflags[i] = 5'h0;
if (a_type_s0[i].is_nan || b_type_s0[i].is_nan) begin
fcmp_res[i] = 32'h0;
@@ -182,7 +182,7 @@ module VX_fp_ncomp #(
fcmp_res[i] = {31'h0, (a_smaller_s0[i] & ~ab_equal_s0[i])};
end
end
`FRM_RDN: begin // EQ
`INST_FRM_RDN: begin // EQ
fcmp_fflags[i] = 5'h0;
if (a_type_s0[i].is_nan || b_type_s0[i].is_nan) begin
fcmp_res[i] = 32'h0;
@@ -207,11 +207,11 @@ module VX_fp_ncomp #(
for (genvar i = 0; i < LANES; i++) begin
always @(*) begin
case (op_type_s0)
`FPU_CLASS: begin
`INST_FPU_CLASS: begin
tmp_result[i] = fclass_mask[i];
tmp_fflags[i] = 'x;
end
`FPU_CMP: begin
`INST_FPU_CMP: begin
tmp_result[i] = fcmp_res[i];
tmp_fflags[i] = fcmp_fflags[i];
end
@@ -238,15 +238,15 @@ module VX_fp_ncomp #(
end
end
wire has_fflags_s0 = ((op_type_s0 == `FPU_MISC)
&& (frm_s0 == 3 // MIN
|| frm_s0 == 4)) // MAX
|| (op_type_s0 == `FPU_CMP); // CMP
wire has_fflags_s0 = ((op_type_s0 == `INST_FPU_MISC)
&& (frm_s0 == 3 // MIN
|| frm_s0 == 4)) // MAX
|| (op_type_s0 == `INST_FPU_CMP); // CMP
assign stall = ~ready_out && valid_out;
VX_pipe_register #(
.DATAW (1 + TAGW + (LANES * 32) + 1 + (LANES * `FFG_BITS)),
.DATAW (1 + TAGW + (LANES * 32) + 1 + (LANES * `FFLAGS_BITS)),
.RESETW (1)
) pipe_reg1 (
.clk (clk),

12
hw/rtl/fp_cores/VX_fp_rounding.v
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@@ -34,7 +34,7 @@ module VX_fp_rounding #(
always @(*) begin
case (rnd_mode_i)
`FRM_RNE: // Decide accoring to round/sticky bits
`INST_FRM_RNE: // Decide accoring to round/sticky bits
case (round_sticky_bits_i)
2'b00,
2'b01: round_up = 1'b0; // < ulp/2 away, round down
@@ -42,10 +42,10 @@ module VX_fp_rounding #(
2'b11: round_up = 1'b1; // > ulp/2 away, round up
default: round_up = 1'bx;
endcase
`FRM_RTZ: round_up = 1'b0; // always round down
`FRM_RDN: round_up = (| round_sticky_bits_i) & sign_i; // to 0 if +, away if -
`FRM_RUP: round_up = (| round_sticky_bits_i) & ~sign_i; // to 0 if -, away if +
`FRM_RMM: round_up = round_sticky_bits_i[1]; // round down if < ulp/2 away, else up
`INST_FRM_RTZ: round_up = 1'b0; // always round down
`INST_FRM_RDN: round_up = (| round_sticky_bits_i) & sign_i; // to 0 if +, away if -
`INST_FRM_RUP: round_up = (| round_sticky_bits_i) & ~sign_i; // to 0 if -, away if +
`INST_FRM_RMM: round_up = round_sticky_bits_i[1]; // round down if < ulp/2 away, else up
default: round_up = 1'bx; // propagate x
endcase
end
@@ -58,7 +58,7 @@ module VX_fp_rounding #(
// In case of effective subtraction (thus signs of addition operands must have differed) and a
// true zero result, the result sign is '-' in case of RDN and '+' for other modes.
assign sign_o = (exact_zero_o && effective_subtraction_i) ? (rnd_mode_i == `FRM_RDN)
assign sign_o = (exact_zero_o && effective_subtraction_i) ? (rnd_mode_i == `INST_FRM_RDN)
: sign_i;
endmodule

2
hw/rtl/fp_cores/VX_fp_sqrt.v
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@@ -16,7 +16,7 @@ module VX_fp_sqrt #(
input wire [TAGW-1:0] tag_in,
input wire [`FRM_BITS-1:0] frm,
input wire [`INST_FRM_BITS-1:0] frm,
input wire [LANES-1:0][31:0] dataa,
output wire [LANES-1:0][31:0] result,

34
hw/rtl/fp_cores/VX_fpu_dpi.v
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@@ -14,8 +14,8 @@ module VX_fpu_dpi #(
input wire [TAGW-1:0] tag_in,
input wire [`FPU_BITS-1:0] op_type,
input wire [`MOD_BITS-1:0] frm,
input wire [`INST_FPU_BITS-1:0] op_type,
input wire [`INST_MOD_BITS-1:0] frm,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
@@ -76,21 +76,21 @@ module VX_fpu_dpi #(
is_fsgnjx = 0;
case (op_type)
`FPU_ADD: begin core_select = FPU_FMA; is_fadd = 1; end
`FPU_SUB: begin core_select = FPU_FMA; is_fsub = 1; end
`FPU_MUL: begin core_select = FPU_FMA; is_fmul = 1; end
`FPU_MADD: begin core_select = FPU_FMA; is_fmadd = 1; end
`FPU_MSUB: begin core_select = FPU_FMA; is_fmsub = 1; end
`FPU_NMADD: begin core_select = FPU_FMA; is_fnmadd = 1; end
`FPU_NMSUB: begin core_select = FPU_FMA; is_fnmsub = 1; end
`FPU_DIV: begin core_select = FPU_DIV; end
`FPU_SQRT: begin core_select = FPU_SQRT; end
`FPU_CVTWS: begin core_select = FPU_CVT; is_ftoi = 1; end
`FPU_CVTWUS:begin core_select = FPU_CVT; is_ftou = 1; end
`FPU_CVTSW: begin core_select = FPU_CVT; is_itof = 1; end
`FPU_CVTSWU:begin core_select = FPU_CVT; is_utof = 1; end
`FPU_CLASS: begin core_select = FPU_NCP; is_fclss = 1; end
`FPU_CMP: begin core_select = FPU_NCP;
`INST_FPU_ADD: begin core_select = FPU_FMA; is_fadd = 1; end
`INST_FPU_SUB: begin core_select = FPU_FMA; is_fsub = 1; end
`INST_FPU_MUL: begin core_select = FPU_FMA; is_fmul = 1; end
`INST_FPU_MADD: begin core_select = FPU_FMA; is_fmadd = 1; end
`INST_FPU_MSUB: begin core_select = FPU_FMA; is_fmsub = 1; end
`INST_FPU_NMADD: begin core_select = FPU_FMA; is_fnmadd = 1; end
`INST_FPU_NMSUB: begin core_select = FPU_FMA; is_fnmsub = 1; end
`INST_FPU_DIV: begin core_select = FPU_DIV; end
`INST_FPU_SQRT: begin core_select = FPU_SQRT; end
`INST_FPU_CVTWS: begin core_select = FPU_CVT; is_ftoi = 1; end
`INST_FPU_CVTWUS:begin core_select = FPU_CVT; is_ftou = 1; end
`INST_FPU_CVTSW: begin core_select = FPU_CVT; is_itof = 1; end
`INST_FPU_CVTSWU:begin core_select = FPU_CVT; is_utof = 1; end
`INST_FPU_CLASS: begin core_select = FPU_NCP; is_fclss = 1; end
`INST_FPU_CMP: begin core_select = FPU_NCP;
is_fle = (frm == 0);
is_flt = (frm == 1);
is_feq = (frm == 2);

30
hw/rtl/fp_cores/VX_fpu_fpga.v
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@@ -11,8 +11,8 @@ module VX_fpu_fpga #(
input wire [TAGW-1:0] tag_in,
input wire [`FPU_BITS-1:0] op_type,
input wire [`MOD_BITS-1:0] frm,
input wire [`INST_FPU_BITS-1:0] op_type,
input wire [`INST_MOD_BITS-1:0] frm,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
@@ -54,19 +54,19 @@ module VX_fpu_fpga #(
is_itof = 0;
is_signed = 0;
case (op_type)
`FPU_ADD: begin core_select = FPU_FMA; end
`FPU_SUB: begin core_select = FPU_FMA; do_sub = 1; end
`FPU_MUL: begin core_select = FPU_FMA; do_neg = 1; end
`FPU_MADD: begin core_select = FPU_FMA; do_madd = 1; end
`FPU_MSUB: begin core_select = FPU_FMA; do_madd = 1; do_sub = 1; end
`FPU_NMADD: begin core_select = FPU_FMA; do_madd = 1; do_neg = 1; end
`FPU_NMSUB: begin core_select = FPU_FMA; do_madd = 1; do_sub = 1; do_neg = 1; end
`FPU_DIV: begin core_select = FPU_DIV; end
`FPU_SQRT: begin core_select = FPU_SQRT; end
`FPU_CVTWS: begin core_select = FPU_CVT; is_signed = 1; end
`FPU_CVTWUS: begin core_select = FPU_CVT; end
`FPU_CVTSW: begin core_select = FPU_CVT; is_itof = 1; is_signed = 1; end
`FPU_CVTSWU: begin core_select = FPU_CVT; is_itof = 1; end
`INST_FPU_ADD: begin core_select = FPU_FMA; end
`INST_FPU_SUB: begin core_select = FPU_FMA; do_sub = 1; end
`INST_FPU_MUL: begin core_select = FPU_FMA; do_neg = 1; end
`INST_FPU_MADD: begin core_select = FPU_FMA; do_madd = 1; end
`INST_FPU_MSUB: begin core_select = FPU_FMA; do_madd = 1; do_sub = 1; end
`INST_FPU_NMADD: begin core_select = FPU_FMA; do_madd = 1; do_neg = 1; end
`INST_FPU_NMSUB: begin core_select = FPU_FMA; do_madd = 1; do_sub = 1; do_neg = 1; end
`INST_FPU_DIV: begin core_select = FPU_DIV; end
`INST_FPU_SQRT: begin core_select = FPU_SQRT; end
`INST_FPU_CVTWS: begin core_select = FPU_CVT; is_signed = 1; end
`INST_FPU_CVTWUS: begin core_select = FPU_CVT; end
`INST_FPU_CVTSW: begin core_select = FPU_CVT; is_itof = 1; is_signed = 1; end
`INST_FPU_CVTSWU: begin core_select = FPU_CVT; is_itof = 1; end
default: begin core_select = FPU_NCP; end
endcase
end

50
hw/rtl/fp_cores/VX_fpu_fpnew.v
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@@ -19,8 +19,8 @@ module VX_fpu_fpnew
input wire [TAGW-1:0] tag_in,
input wire [`FPU_BITS-1:0] op_type,
input wire [`MOD_BITS-1:0] frm,
input wire [`INST_FPU_BITS-1:0] op_type,
input wire [`INST_MOD_BITS-1:0] frm,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
@@ -81,7 +81,7 @@ module VX_fpu_fpnew
fpnew_pkg::status_t [`NUM_THREADS-1:0] fpu_status;
reg [FOP_BITS-1:0] fpu_op;
reg [`FRM_BITS-1:0] fpu_rnd;
reg [`INST_FRM_BITS-1:0] fpu_rnd;
reg fpu_op_mod;
reg fpu_has_fflags, fpu_has_fflags_out;
@@ -95,38 +95,38 @@ module VX_fpu_fpnew
fpu_operands[2] = datac;
case (op_type)
`FPU_ADD: begin
`INST_FPU_ADD: begin
fpu_op = fpnew_pkg::ADD;
fpu_operands[1] = dataa;
fpu_operands[2] = datab;
end
`FPU_SUB: begin
`INST_FPU_SUB: begin
fpu_op = fpnew_pkg::ADD;
fpu_operands[1] = dataa;
fpu_operands[2] = datab;
fpu_op_mod = 1;
end
`FPU_MUL: begin fpu_op = fpnew_pkg::MUL; end
`FPU_DIV: begin fpu_op = fpnew_pkg::DIV; end
`FPU_SQRT: begin fpu_op = fpnew_pkg::SQRT; end
`FPU_MADD: begin fpu_op = fpnew_pkg::FMADD; end
`FPU_MSUB: begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = 1; end
`FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = 1; end
`FPU_NMSUB: begin fpu_op = fpnew_pkg::FNMSUB; end
`FPU_CVTWS: begin fpu_op = fpnew_pkg::F2I; end
`FPU_CVTWUS:begin fpu_op = fpnew_pkg::F2I; fpu_op_mod = 1; end
`FPU_CVTSW: begin fpu_op = fpnew_pkg::I2F; end
`FPU_CVTSWU:begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = 1; end
`FPU_CLASS: begin fpu_op = fpnew_pkg::CLASSIFY; fpu_has_fflags = 0; end
`FPU_CMP: begin fpu_op = fpnew_pkg::CMP; end
`FPU_MISC: begin
`INST_FPU_MUL: begin fpu_op = fpnew_pkg::MUL; end
`INST_FPU_DIV: begin fpu_op = fpnew_pkg::DIV; end
`INST_FPU_SQRT: begin fpu_op = fpnew_pkg::SQRT; end
`INST_FPU_MADD: begin fpu_op = fpnew_pkg::FMADD; end
`INST_FPU_MSUB: begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = 1; end
`INST_FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = 1; end
`INST_FPU_NMSUB: begin fpu_op = fpnew_pkg::FNMSUB; end
`INST_FPU_CVTWS: begin fpu_op = fpnew_pkg::F2I; end
`INST_FPU_CVTWUS:begin fpu_op = fpnew_pkg::F2I; fpu_op_mod = 1; end
`INST_FPU_CVTSW: begin fpu_op = fpnew_pkg::I2F; end
`INST_FPU_CVTSWU:begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = 1; end
`INST_FPU_CLASS: begin fpu_op = fpnew_pkg::CLASSIFY; fpu_has_fflags = 0; end
`INST_FPU_CMP: begin fpu_op = fpnew_pkg::CMP; end
`INST_FPU_MISC: begin
case (frm)
0: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RNE; fpu_has_fflags = 0; end
1: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RTZ; fpu_has_fflags = 0; end
2: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RDN; fpu_has_fflags = 0; end
3: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RNE; end
4: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RTZ; end
default: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RUP; fpu_has_fflags = 0; end
0: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RNE; fpu_has_fflags = 0; end
1: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RTZ; fpu_has_fflags = 0; end
2: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RDN; fpu_has_fflags = 0; end
3: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `INST_FRM_RNE; end
4: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `INST_FRM_RTZ; end
default: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RUP; fpu_has_fflags = 0; end
endcase
end
default:;