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instruction decode refactoring fixing naming collision

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This commit is contained in:
Blaise Tine
2021-08-29 20:07:34 -07:00
parent 90b50277d0
commit a801a16062
32 changed files with 434 additions and 437 deletions
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14
hw/rtl/VX_muldiv.v
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@@ -5,7 +5,7 @@ module VX_muldiv (
input wire reset,
// Inputs
input wire [`MUL_BITS-1:0] alu_op,
input wire [`INST_MUL_BITS-1:0] alu_op,
input wire [`NW_BITS-1:0] wid_in,
input wire [`NUM_THREADS-1:0] tmask_in,
input wire [31:0] PC_in,
@@ -29,7 +29,7 @@ module VX_muldiv (
input wire ready_out
);
wire is_div_op = `MUL_IS_DIV(alu_op);
wire is_div_op = `INST_MUL_IS_DIV(alu_op);
wire [`NUM_THREADS-1:0][31:0] mul_result;
wire [`NW_BITS-1:0] mul_wid_out;
@@ -44,9 +44,9 @@ module VX_muldiv (
wire mul_valid_in = valid_in && !is_div_op;
wire mul_ready_in = ~stall_out || ~mul_valid_out;
wire is_mulh_in = (alu_op != `MUL_MUL);
wire is_signed_mul_a = (alu_op != `MUL_MULHU);
wire is_signed_mul_b = (alu_op != `MUL_MULHU && alu_op != `MUL_MULHSU);
wire is_mulh_in = (alu_op != `INST_MUL_MUL);
wire is_signed_mul_a = (alu_op != `INST_MUL_MULHU);
wire is_signed_mul_b = (alu_op != `INST_MUL_MULHU && alu_op != `INST_MUL_MULHSU);
`ifdef IMUL_DPI
@@ -123,8 +123,8 @@ module VX_muldiv (
wire [`NR_BITS-1:0] div_rd_out;
wire div_wb_out;
wire is_rem_op_in = (alu_op == `MUL_REM) || (alu_op == `MUL_REMU);
wire is_signed_div = (alu_op == `MUL_DIV) || (alu_op == `MUL_REM);
wire is_rem_op_in = (alu_op == `INST_MUL_REM) || (alu_op == `INST_MUL_REMU);
wire is_signed_div = (alu_op == `INST_MUL_DIV) || (alu_op == `INST_MUL_REM);
wire div_valid_in = valid_in && is_div_op;
wire div_ready_out = ~stall_out && ~mul_valid_out; // arbitration prioritizes MUL
wire div_ready_in;