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set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18

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This commit is contained in:
Blaise Tine
2020-06-29 08:03:19 -07:00
parent d33916f1e0
commit a70562d386
8 changed files with 40 additions and 11 deletions
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4
driver/rtlsim/Makefile
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@@ -16,8 +16,8 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
#DBG_FLAGS += $(DBG_PRINT_FLAGS) #DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CORE_REQ_INFO DBG_FLAGS += -DDBG_CORE_REQ_INFO
#CONFIGS += -DNUM_CLUSTERS=2 -DNUM_CORES=4 #CONFIGS += -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=4 #CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 #CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2
#DEBUG=1 #DEBUG=1

27
hw/opae/Makefile
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@@ -2,7 +2,7 @@ ASE_BUILD_DIR=build_ase
FPGA_BUILD_DIR=build_fpga FPGA_BUILD_DIR=build_fpga
all: ase-2c all: ase-1c
ase-1c: setup-ase-1c ase-1c: setup-ase-1c
make -C $(ASE_BUILD_DIR)_1c make -C $(ASE_BUILD_DIR)_1c
@@ -10,47 +10,72 @@ ase-1c: setup-ase-1c
ase-2c: setup-ase-2c ase-2c: setup-ase-2c
make -C $(ASE_BUILD_DIR)_2c make -C $(ASE_BUILD_DIR)_2c
ase-4c: setup-ase-4c
make -C $(ASE_BUILD_DIR)_4c
setup-ase-1c: $(ASE_BUILD_DIR)_1c/Makefile setup-ase-1c: $(ASE_BUILD_DIR)_1c/Makefile
setup-ase-2c: $(ASE_BUILD_DIR)_2c/Makefile setup-ase-2c: $(ASE_BUILD_DIR)_2c/Makefile
setup-ase-4c: $(ASE_BUILD_DIR)_4c/Makefile
$(ASE_BUILD_DIR)_1c/Makefile: $(ASE_BUILD_DIR)_1c/Makefile:
afu_sim_setup -s sources_1c.txt $(ASE_BUILD_DIR)_1c afu_sim_setup -s sources_1c.txt $(ASE_BUILD_DIR)_1c
$(ASE_BUILD_DIR)_2c/Makefile: $(ASE_BUILD_DIR)_2c/Makefile:
afu_sim_setup -s sources_2c.txt $(ASE_BUILD_DIR)_2c afu_sim_setup -s sources_2c.txt $(ASE_BUILD_DIR)_2c
$(ASE_BUILD_DIR)_4c/Makefile:
afu_sim_setup -s sources_4c.txt $(ASE_BUILD_DIR)_4c
fpga-1c: setup-fpga-1c fpga-1c: setup-fpga-1c
cd $(FPGA_BUILD_DIR)_1c && qsub-synth cd $(FPGA_BUILD_DIR)_1c && qsub-synth
fpga-2c: setup-fpga-2c fpga-2c: setup-fpga-2c
cd $(FPGA_BUILD_DIR)_2c && qsub-synth cd $(FPGA_BUILD_DIR)_2c && qsub-synth
fpga-4c: setup-fpga-4c
cd $(FPGA_BUILD_DIR)_4c && qsub-synth
setup-fpga-1c: $(FPGA_BUILD_DIR)_1c/build/dcp.qpf setup-fpga-1c: $(FPGA_BUILD_DIR)_1c/build/dcp.qpf
setup-fpga-2c: $(FPGA_BUILD_DIR)_2c/build/dcp.qpf setup-fpga-2c: $(FPGA_BUILD_DIR)_2c/build/dcp.qpf
setup-fpga-4c: $(FPGA_BUILD_DIR)_4c/build/dcp.qpf
$(FPGA_BUILD_DIR)_1c/build/dcp.qpf: $(FPGA_BUILD_DIR)_1c/build/dcp.qpf:
afu_synth_setup -s sources_1c.txt $(FPGA_BUILD_DIR)_1c afu_synth_setup -s sources_1c.txt $(FPGA_BUILD_DIR)_1c
$(FPGA_BUILD_DIR)_2c/build/dcp.qpf: $(FPGA_BUILD_DIR)_2c/build/dcp.qpf:
afu_synth_setup -s sources_2c.txt $(FPGA_BUILD_DIR)_2c afu_synth_setup -s sources_2c.txt $(FPGA_BUILD_DIR)_2c
$(FPGA_BUILD_DIR)_4c/build/dcp.qpf:
afu_synth_setup -s sources_4c.txt $(FPGA_BUILD_DIR)_4c
run-ase-1c: run-ase-1c:
cd $(ASE_BUILD_DIR)_1c && make sim cd $(ASE_BUILD_DIR)_1c && make sim
run-ase-2c: run-ase-2c:
cd $(ASE_BUILD_DIR)_2c && make sim cd $(ASE_BUILD_DIR)_2c && make sim
run-ase-4c:
cd $(ASE_BUILD_DIR)_4c && make sim
clean-ase-1c: clean-ase-1c:
rm -rf $(ASE_BUILD_DIR)_1c rm -rf $(ASE_BUILD_DIR)_1c
clean-ase-2c: clean-ase-2c:
rm -rf $(ASE_BUILD_DIR)_2c rm -rf $(ASE_BUILD_DIR)_2c
clean-ase-4c:
rm -rf $(ASE_BUILD_DIR)_4c
clean-fpga-1c: clean-fpga-1c:
rm -rf $(FPGA_BUILD_DIR)_1c rm -rf $(FPGA_BUILD_DIR)_1c
clean-fpga-2c: clean-fpga-2c:
rm -rf $(FPGA_BUILD_DIR)_2c rm -rf $(FPGA_BUILD_DIR)_2c
clean-fpga-4c:
rm -rf $(FPGA_BUILD_DIR)_4c

4
hw/opae/sources_4c.txt Normal file
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@@ -0,0 +1,4 @@
+define+NUM_CORES=4
+define+L2_ENABLE=0
C:sources.txt

4
hw/rtl/VX_alu_unit.v
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@@ -13,8 +13,8 @@ module VX_alu_unit (
output reg [31:0] alu_result, output reg [31:0] alu_result,
output reg alu_stall output reg alu_stall
); );
localparam DIV_PIPELINE_LEN = 20; localparam DIV_PIPELINE_LEN = 18;
localparam MUL_PIPELINE_LEN = 8; localparam MUL_PIPELINE_LEN = 1;
wire[31:0] div_result_unsigned; wire[31:0] div_result_unsigned;
wire[31:0] div_result_signed; wire[31:0] div_result_signed;

4
hw/rtl/VX_config.vh
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@@ -8,7 +8,7 @@
`endif `endif
`ifndef NUM_CORES `ifndef NUM_CORES
`define NUM_CORES 1 `define NUM_CORES 4
`endif `endif
`ifndef NUM_WARPS `ifndef NUM_WARPS
@@ -52,7 +52,7 @@
`endif `endif
`ifndef L2_ENABLE `ifndef L2_ENABLE
`define L2_ENABLE (`NUM_CORES > 2) `define L2_ENABLE 0
`endif `endif
`ifndef L3_ENABLE `ifndef L3_ENABLE

2
hw/rtl/libs/VX_generic_queue.v
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@@ -3,7 +3,7 @@
module VX_generic_queue #( module VX_generic_queue #(
parameter DATAW, parameter DATAW,
parameter SIZE = 16, parameter SIZE = 16,
parameter BUFFERED_OUTPUT = (SIZE > 8) parameter BUFFERED_OUTPUT = 1
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,

4
hw/simulate/Makefile
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@@ -1,5 +1,5 @@
#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4 #MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1
#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4 #MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1
MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
# control RTL debug print states # control RTL debug print states

2
hw/syn/quartus/project.sdc
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@@ -1,6 +1,6 @@
set_time_format -unit ns -decimal_places 3 set_time_format -unit ns -decimal_places 3
create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}] create_clock -name {clk} -period "200 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]
derive_pll_clocks -create_base_clocks derive_pll_clocks -create_base_clocks
derive_clock_uncertainty derive_clock_uncertainty